S. Yamaguchi

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

0-56 GHz GaAs MESFET gate-line-division distributed baseband amplifier IC with 3D transmission lines

Y. Imai, K. Onodera, S. Kimura, 1997 .

Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node

Hiroshi Kudo, Takashi Suzuki, A. Hasegawa, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores

Hiroshi Kudo, Naoki Nagashima, Ikuhiro Yamamura, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

25 Gbit/s selector module using 0.2 mu m GaAs MESFET technology

K. Murata, M. Togashi, M. Ohhata, 1993 .

46 Gbit/s multiplexer and 40 Gbit/s demultiplexer IC modules using InAlAs/InGaAs/InP HEMTs

Eiichi Sano, Y. Imai, Yohtaro Umeda, 1996 .