H. Fukutome

发表

Comprehensive design methodology of dopant profile to suppress gate-LER-induced threshold voltage variability in 20nm NMOSFETs

W. Fichtner, T. Sugii, S. Satoh, 2006, 2009 Symposium on VLSI Technology.

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

S. Satoh, Y. Momiyama, S. Satoh, 2010, IEEE Electron Device Letters.

(110) NMOSFETs competitive to (001) NMOSFETs: Si migration to create (331) facet and ultra-shallow Al implantation after NiSi formation

S. Satoh, T. Yamamoto, H. Minakata, 2008, 2008 IEEE International Electron Devices Meeting.

Integration Strategy of Embedded SiGe S/D CMOS from Viewpoint of Performance and Cost for 45nm-Node and Beyond

T. Miyashita, Naoyoshi Tamura, Masataka Kase, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Carrier profile designing to suppress systematic Vth variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects

S. Satoh, H. Minakata, Y. Momiyama, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

3 dimensional scaling extensibility on epitaxial source drain strain technology toward Fin FET and beyond

H. Fukutome, S. Maeda, Y. Ko, 2013, 2013 Symposium on VLSI Technology.

Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs

Y. Momiyama, T. Aoyama, Y. Tagawa, 2006, IEEE Transactions on Electron Devices.

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

T. Miyashita, Masaki Yamabe, Tetsu Tanaka, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETs

Y. Momiyama, T. Aoyama, Y. Tagawa, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Fluorine implantation impact in extension region on the electrical performance of sub-50nm P-MOSFETs

H. Nakao, Y. Momiyama, T. Aoyama, 2003, IEEE International Electron Devices Meeting 2003.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

Y. S. Nam, J. H. Lee, K. H. Lee, 2016, 2016 IEEE Symposium on VLSI Technology.

Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs

Tomohiro Kubo, Takayuki Aoyama, Y. Momiyama, 2006, 2006 International Electron Devices Meeting.