D. Velenis

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

E. Beyne, K. Croes, A. Redolfi, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Reliability concerns in copper TSV's: Methods and results

E. Beyne, G. Van der Plas, I. De Wolf, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 Symposium on VLSI Technology.

Electrical characterization method to study barrier integrity in 3D through-silicon vias

K. Croes, M. Stucchi, T. Kauerauf, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Wafer thinning and back side processing to enable 3D stacking

E. Beyne, A. La Manna, M. Detalle, 2012, 2012 4th Electronic System-Integration Technology Conference.

Effects of parameter variations and crosstalk on H-tree clock distribution networks

D. Velenis, I. Chanodia, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices

E. Beyne, M. Detalle, A. La Manna, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Characterization of Impact of Vertical Stress on FinFETs

E. Beyne, I. De Wolf, K. Vanstreels, 2019, 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC).