Jia-Wen Chang

Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips

Tsung-Wei Huang, Tsung-Yi Ho, Sheng-Han Yeh, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Chip-level design and optimization for digital microfluidic biochips

Tsung-Yi Ho, Jia-Wen Chang, Tsung-Wei Huang, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips

Tsung-Wei Huang, Tsung-Yi Ho, Jia-Wen Chang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance

Tsung-Wei Huang, Tsung-Yi Ho, Sheng-Han Yeh, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Recent research and emerging challenges in design and optimization for digital microfluidic biochips

Tsung-Wei Huang, Tsung-Yi Ho, Jia-Wen Chang, 2011, 2011 IEEE International SOC Conference.

An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips

Tsung-Wei Huang, Tsung-Yi Ho, Jia-Wen Chang, 2012, 17th Asia and South Pacific Design Automation Conference.

Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips

Tsung-Wei Huang, Tsung-Yi Ho, Sheng-Han Yeh, 2013, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips

Tsung-Wei Huang, Tsung-Yi Ho, Sheng-Han Yeh, 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..