Jieming Qi

ST-MRAM Fundamentals, Challenges, and Outlook

Xiaohu Zhang, Yaojun Zhang, Tom Andre, 2017, 2017 IEEE International Memory Workshop (IMW).

Electroluminescence from novel porous silicon p-n junction devices

Jieming Qi, Biswajit Das, D. C. Diaz, 1994, Photonics West - Lasers and Applications in Science and Engineering.

A Circuit for Reducing Large Transient Current Effects on Processor Power Grids

Jieming Qi, E. Hailu, D. Boerstler, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

Mounir Meghelli, Michael A. Sorna, Sergey V. Rylov, 2012, IEEE J. Solid State Circuits.

A new test and characterization scheme for 10+ GHz low jitter wide band PLL

Yuichi Goto, Jieming Qi, David W. Boerstler, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Mounir Meghelli, Sergey V. Rylov, Jong-Ru Guo, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A Background Optimization Method for PLL by Measuring Phase

G. Taylor, Jieming Qi, Munehiro Yoshida, 2004 .