Mikael Casse

Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

Maud Vinet, Sylvain Barraud, Gilles Reimbold, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Experimental Investigation of the Tunneling Injection Boosters for Enhanced $I_{ON}$ ETSOI Tunnel FET

Sorin Cristoloveanu, Francois Andrieu, Jean-Michel Hartmann, 2013, IEEE Transactions on Electron Devices.

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Maud Vinet, Claire Fenouillet-Beranger, D. Lafond, 2015 .

Gate-induced floating-body effect in fully-depleted SOI MOSFETs with tunneling oxide and back-gate biasing

G. Reimbold, Claire Fenouillet-Beranger, Sorin Cristoloveanu, 2004 .

From double to triple gate: Modeling junctionless nanowire transistors

Sylvain Barraud, Gilles Reimbold, Olivier Faynot, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Stephane Monfray, Frederic Boeuf, M.-P. Samson, 2013 .

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

G. Reimbold, Hiroshi Iwai, Gerard Ghibaudo, 2013 .