C. Mazure

发表

Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO/sub 2//TiN gate stack down to 15nm gate length

O. Faynot, G. Ghibaudo, F. Andrieu, 2005, 2005 IEEE International SOI Conference Proceedings.

25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack

O. Faynot, F. Andrieu, T. Ernst, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Germanium-on-insulator (GeOI) structures realized by the Smart Cut/spl trade/ technology

C. Mazure, N. Kernevez, C. Morales, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Current status and future perspectives of wafer bonding (Smart Cut/spl trade/) SOI technology

C. Mazure, M. Yoshimi, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

Advanced Simulation for Reliability Optimization of Submicron LDD MOSFETs

C. Mazure, A. Lill, F. Neppl, 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

Low Voltage FeRAMs : Challenges and Solutions for Future Product Applications

C. Mazure, Christine Dehm, W. Hartner, 1999 .

lo" i Active region

C. Mazure, M. Kerber, 1990 .

Smart Cut™ technology provides excellent layer uniformity for fully depleted CMOS

C. Mazure, W. Schwarzenbach, C. Maleville, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Integrated circuits and manufacturing DRAM and NAND flash

C. Mazure, T. Nakabayashi, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Transfer of patterned Si and SiO/sub 2/ layers for the fabrication of patterned and mixed SOI

B. Ghyselen, C. Mazure, N. Kernevez, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Impact of Advanced SOI Substrates on Device Architecture and Design

C. Mazure, J. Wasselin, 2006, 2006 IEEE International Conference on IC Design and Technology.

Advanced SOI substrate manufacturing

C. Mazure, C. Maleville, I. Cayrefourcq, 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

Advanced Substrate Engineering for the Nanotechnology Era

C. Mazure, 2006, 2006 International Symposium on VLSI Technology, Systems, and Applications.

Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion

C. Mazure, F. Lau, M. Orlowski, 1987, 1987 International Electron Devices Meeting.

Hot carrier hardness analysis of submicrometer LDD devices

Marius K. Orlowski, C. Mazure, A. Lill, 1991 .

Matching behavior of analog FDSOI n-MOS-transistors under large backgate voltage swing operating conditions

G. Reimbold, C. Mazure, F. Allain, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFETS

C. Gunderson, C. Mazure, J. Fitch, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Improvement of latchup hardness by geometry and technology tuning

C. Mazure, D. Takacs, W. Reczek, 1988 .

Polysilicon encapsulated local oxidation

C. Mazure, C. Mazure, S.S. Roth, 1991, IEEE Electron Device Letters.

Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

O. Rozeau, O. Faynot, M. Vinet, 2014, 2014 IEEE International Electron Devices Meeting.

Overview of FDSOI technology from substrate to device

O. Faynot, F. Andrieu, C. Mazure, 2009, 2009 International Semiconductor Device Research Symposium.

Width-independent narrow nMOSFET reliability by split-well drive-in

C. Mazure, A. Lill, C. Zeller, 1990, IEEE Electron Device Letters.

Guidelines for reverse short-channel behavior

C. Mazure, M. Orlowski, 1989, IEEE Electron Device Letters.

Status of device mobility enhancement through strained silicon engineering

C. Mazure, I. Cayrefourcq, 2005, 2005 IEEE International SOI Conference Proceedings.

Alternative dielectrics for advanced SOI MOSFETs: thermal properties and short channel effects

C. Mazure, H. Iwai, S. Cristoloveanu, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

A model for phosphorus segregation at the silicon-silicon dioxide interface

Marius K. Orlowski, C. Mazure, F. Lau, 1989 .

Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility

C. Mazure, C.R. Cleavelin, P. Patruno, 2006, IEEE Electron Device Letters.

Ultra-scaled Z-RAM cell

C. Mazure, S. Selberherr, W. Xiong, 2008, 2008 IEEE International SOI Conference.

Excellent silicon thickness uniformity on Ultra-Thin SOI for controlling Vt variation of FDSOI

C. Mazure, W. Schwarzenbach, F. Boedt, 2011, 2011 IEEE International Conference on IC Design & Technology.

Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

J. Conner, C. Mazure, S. Murphy, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Current status and possibilities of wafer-bonding-based SOI technology in 45nm or below CMOS LSIs

C. Mazure, I. Cayrefourcq, M. Yoshimi, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.