Rajendra Kumar Nagaria

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Shipra Upadhyay, Rajendra Kumar Nagaria, Ram Awadh Mishra, 2013, VLSI Design.

On the New Design of sinusoid voltage Controlled oscillators Using Multiplier in CFA-Based Double Integrator Loop

Subodh Wairya, Rakesh Kumar Singh, Rajendra Kumar Nagaria, 2010, J. Circuits Syst. Comput..

Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit

Ankur Kumar, Avaneesh K. Dubey, Rajendra Kumar Nagaria, 2021 .

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

Rajendra Kumar Nagaria, Pratosh Kumar Pal, 2020, Integr..

Energy Efficient Angle based Route Selection in 3D Wireless Sensor Networks

Rama Shankar Yadav, Naveen Kumar Gupta, Rajendra Kumar Nagaria, 2019, 2019 58th Annual Conference of the Society of Instrument and Control Engineers of Japan (SICE).

Voltage comparison based high speed & low power domino circuit for wide fan-in gates

Sankit R. Kassa, Avaneesh K. Dubey, Rajendra Kumar Nagaria, 2016, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Sudarshan Tiwari, Subodh Wairya, Rajendra Kumar Nagaria, 2012, VLSI Design.

An Angular 3D Path Selection Protocol in Wireless Sensor Networks

Rama Shankar Yadav, Rajendra Kumar Nagaria, Naveen Kumar Gupta, 2021, Open Comput. Sci..

NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS

Subodh Wairya, Rajendra Kumar Nagaria, R. Nagaria, 2011 .