Ram Awadh Mishra

发表

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Shipra Upadhyay, Rajendra Kumar Nagaria, Ram Awadh Mishra, 2013, VLSI Design.

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Sudarshan Tiwari, Sanjeev Rai, Ram Awadh Mishra, 2013 .

Area Efficient Sparse Modulo 2 n - 3 Adder

Ram Awadh Mishra, Ritesh Kumar Jaiswal, Chatla Naveen Kumar, 2016 .

Studies on the simulation and microcontroller implementation of some residue number system based building blocks for applications in digital signal processing

Ram Awadh Mishra, 2005 .

Conditional Precharge Dynamic Buffer Circuit

V. Krishna Rao Kandanvli, R. K. Nagaria, Ram Awadh Mishra, 2012 .

Design of High-performance Digital Logic Circuits based on FinFET Technology

Ram Awadh Mishra, V Narendar, R WanjulDattatray, 2012 .

Design of New Low Leakage Power Domino XOR Circuit

R. K. Nagaria, Ram Awadh Mishra, Manish Tiwari, 2013 .

Area Efficient Memoryless Reverse Converter for New Four Moduli Set {2n-1, 2n-1, 2n+1, 22n+1-1}

Raj Kumar, Ram Awadh Mishra, Ritesh Kumar Jaiswal, 2017, J. Circuits Syst. Comput..

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

Ram Awadh Mishra, Raj Kumar, 2021 .

Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)

Ram Awadh Mishra, Vadthiya Narendar, R. Mishra, 2015 .