P. Ribot

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

Alain Chantre, Daniel Gloria, M. Laurens, 1999 .

Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process

T. Skotnicki, R. Pantel, R. Gwoziecki, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

T. Skotnicki, S. Monfray, D. Dutartre, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A Self-Aligned, Electrically Separable Double-Gate MOS Transistor Technology for Dynamic Threshold Voltage Application

Michel Haond, Stephane Monfray, Thomas Skotnicki, 2003 .

High performance 40 nm vertical MOSFET within a conventional CMOS process flow

T. Skotnicki, A. Villaret, M. Jurczak, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

Stephane Monfray, Thomas Skotnicki, M. Jurczak, 2001 .

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

M. Haond, T. Skotnicki, S. Monfray, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Dielectric pockets – a new concept of the junctions for deca-nanometric CMOS devices

T. Skotnicki, S. Monfray, D. Dutartre, 2000, 30th European Solid-State Device Research Conference.