M. Wilson

An NMOS VLSI process for fabrication of a 32b CPU chip

S. Seccombe, J. Mikkelson, L. Hall, 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A high density 0.10 /spl mu/m CMOS technology using low K dielectric and copper interconnect

D. Reber, G. Yeap, M. Aminpur, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).