M. Usami

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Keiichi Higeta, M. Usami, Masayuki Ohayashi, 1996 .

A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram

Keiichi Higeta, M. Usami, Masayuki Ohayashi, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

High-speed SRAM Circuit Technology「A 1.8ns Access, 550MHz 4.5Mb CMOS SRAM」「Synonym Hit RAM: A 500MHz 1.5ns CMOS SRAM Macro with 576b Parallel Comparison and Parity Check Functions」

Keiichi Higeta, M. Usami, Y. Fujimura, 1998 .

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

Keiichi Higeta, M. Usami, M. Nishiyama, 2000 .

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

Keiichi Higeta, M. Usami, Masayuki Ohayashi, 1995, Proceedings of Bipolar/Bicmos Circuits and Technology Meeting.

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

Keiichi Higeta, M. Usami, Masayuki Ohayashi, 1995 .