Romesh Kumar Nandwana

发表

A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2017, IEEE Journal of Solid-State Circuits.

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2019, IEEE Journal of Solid-State Circuits.

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Ahmed Elkholy, Tejasvi Anand, Pavan Kumar Hanumolu, 2017, IEEE J. Solid State Circuits.

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter

Pavan Kumar Hanumolu, Saurabh Saxena, Romesh Kumar Nandwana, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Clock multiplication techniques for high-speed I/Os

Romesh Kumar Nandwana, 2017 .

A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

Amr Elshazly, Pavan Kumar Hanumolu, Kartikeya Mayaram, 2013, 2013 Symposium on VLSI Circuits.

A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Amr Elshazly, Pavan Kumar Hanumolu, Kartikeya Mayaram, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Daniel Coombs, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2017, IEEE Journal of Solid-State Circuits.

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2015, IEEE Journal of Solid-State Circuits.

A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/ $\lambda$ PAM-4 Optical Links

Romesh Kumar Nandwana, Richard Booth, Alexander Kurylak, 2019, IEEE Journal of Solid-State Circuits.

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Ahmed Elkholy, Pavan Kumar Hanumolu, Guanghua Shu, 2017, IEEE Journal of Solid-State Circuits.

A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu, 2016, IEEE Journal of Solid-State Circuits.

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS

Pavan Kumar Hanumolu, Guanghua Shu, Junheng Zhu, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS

Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski, Qadeer Ahmad Khan, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator

Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski, Qadeer Ahmad Khan, 2015, IEEE Journal of Solid-State Circuits.

A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis

Pavan Kumar Hanumolu, Saurabh Saxena, Romesh Kumar Nandwana, 2014, IEEE Journal of Solid-State Circuits.

A 0.7V time-based inductor for fully integrated low bandwidth filter applications

Pavan Kumar Hanumolu, Bibhudatta Sahoo, Guanghua Shu, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling

Ahmed Elkholy, Pavan Kumar Hanumolu, Romesh Kumar Nandwana, 2021, IEEE Journal of Solid-State Circuits.