J.-H. Ku

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

S. Choi, J. Ku, N. Lee, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Highly manufacturable sub-100 nm DRAM integrated with full functionality

J.K. Cho, J.J. Lee, S. Choi, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

Influence of annealing condition on the properties of sputtered hafnium oxide

Jung Ho Yoo, Hyo-Jick Choi, Jooho Moon, 2002 .

65nm cmos technology for low power applications

M. Sherony, T. Schiml, A. Cowley, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

H.S. Kim, J.M. Park, Y.S. Hwang, 2002, Digest. International Electron Devices Meeting,.