C.H. Diaz

Temperature dependent channel backscattering coefficients in nanoscale MOSFETs

Chih-Sheng Chang, Ming-Jer Chen, Huan-Tsung Huang, 2002, Digest. International Electron Devices Meeting,.

A 65nm node strained SOI technology with slim spacer

Chenming Hu, Tsai-Sheng Gau, Yee-Chia Yeo, 2003, IEEE International Electron Devices Meeting 2003.

Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs

Chih-Sheng Chang, Ming-Jer Chen, C.H. Diaz, 2005, IEEE Transactions on Electron Devices.

45nm High-k/Metal-Gate CMOS Technology for GPU/NPU Applications with Highest PFET Performance

C.C. Chen, H.T. Huang, K. Goto, 2007, 2007 IEEE International Electron Devices Meeting.

Monolithic CMOS distributed amplifier and oscillator

B. Kleveland, S.S. Wong, L. Madden, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

High-Performance PMOS Devices on (110)/<111'> Substrate/Channel with Multiple Stressors

Mong-Song Liang, H.C.-H. Wang, Tze-Liang Lee, 2006, 2006 International Electron Devices Meeting.

Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications

S.Z. Chang, B.L. Lin, J.J. Liaw, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Bulk CMOS technology for SOC

C.H. Diaz, 2002, Extended Abstracts of the Third International Workshop on Junction Technology, 2002. IWJT..

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

Chenming Hu, Tsai-Sheng Gau, Jaw-Jung Shin, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Impact of STI mechanical stress in highly scaled MOSFETs

H.C. Lin, C.H. Lee, C.H. Diaz, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Characterization of polysilicon resistors in sub-0.25 μm CMOS ULSI applications

Chin-Chuan Cheng, Shyh-Chyi Wong, K. Thei, 2001, IEEE Electron Device Letters.