V. Kilchytska

发表

D. Flandre, J. Raskin, M. Haond, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs

Denis Flandre, Cor Claeys, Eddy Simoen, 2012, Microelectron. Reliab..

Effect of high-energy neutrons on MuGFETs

Denis Flandre, Otilia Militaru, Nadine Collaert, 2010 .

Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Denis Flandre, Antonio Cerdeira, Jean-Pierre Raskin, 2007 .

ON DOUBLE-GATE MOSFETS AND FINFETS MODELING

D. Flandre, B. Iñíguez, M. Estrada, 2014 .

High-temperature perspectives of UTB SOI MOSFETs

O. Faynot, F. Andrieu, D. Flandre, 2011, Ulis 2011 Ultimate Integration on Silicon.

Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures

Denis Flandre, Nadine Collaert, Malgorzata Jurczak, 2007 .

3-D Analytical Models for the Short-Channel Effect Parameters in Undoped FinFET Devices

D. Flandre, B. Iñíguez, J. Roig, 2007 .

A 3-D Analytical Physically Based Model for the Subthreshold Swing in Undoped Trigate FinFETs

D. Flandre, B. Iñíguez, V. Kilchytska, 2007, IEEE Transactions on Electron Devices.

Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects

D. Flandre, N. Collaert, D. Lederer, 2005, IEEE Electron Device Letters.

Impact of neutron irradiation on oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

D. Flandre, C. Roda Neve, D. Lederer, 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications

Denis Flandre, V. Pathirana, C. W. Chan, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

D. Flandre, M. Haond, N. Planes, 2017 .

Analysis and modelling of temperature effect on DIBL in UTBB FD SOI MOSFETs

D. Flandre, M. Haond, N. Planes, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Revised split C-V technique for mobility investigation in advanced devices

D. Flandre, J. Raskin, N. Collaert, 2005, 2005 IEEE International SOI Conference Proceedings.

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs

Denis Flandre, El Hafed Boufouss, Joaquín Alvarado, 2010, Microelectron. Reliab..

Time and Frequency Domain Characterization of Transistor Self-Heating

V. Kilchytska, S. Makovejev, S. H. Olsen, 2013, IEEE Transactions on Electron Devices.

A method for threshold voltage extraction in junctionless MOSFETs using the derivative of transconductance-to-current ratio

D. Flandre, S. Barraud, T. Rudenko, 2020, Solid-State Electronics.

Design and fabrication of a power Si/SiC LDMOSFET for high temperature applications

C. W. Chan, D. Flandre, J. Gardner, 2017 .

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

D. Flandre, A. Cerdeira, V. Kilchytska, 2006, IEEE Transactions on Electron Devices.

High-temperature instability processes in SOI structures and MOSFETs

J. Colinge, A. Nazarov, V. Kilchytska, 2001 .

Improvement of high-frequency FinFET performance by fin width engineering

V. Kilchytska, D. Flandre, J.-P Raskin, 2012, 2012 IEEE International SOI Conference (SOI).

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

B. Kazemi Esfeh, N. Planes, M. Haond, 2019, Solid-State Electronics.

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

Denis Flandre, Jean-Pierre Raskin, Joaquín Alvarado, 2011, Microelectron. Reliab..

Characterization and modelling of single event transients in LDMOS-SOI FETs

Denis Flandre, El Hafed Boufouss, Joaquín Alvarado, 2011, Microelectron. Reliab..

Low-power dihexylquaterthiophene-based thin film transistors for analog applications.

D. Flandre, B. Nysten, A. Jonas, 2008 .

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

D. Flandre, J. Gardner, P. Mawby, 2017 .

28 FDSOI analog and RF Figures of Merit at cryogenic temperatures

N. Planes, M. Haond, D. Flandre, 2018, 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

28 nm FD SOI Technology Platform RF FoM

V. Kilchytska, N. Planes, M. Haond, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Perspective of FinFETs for analog applications

V. Kilchytska, J.-P. Raskin, D. Flandre, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements

Denis Flandre, Jean-Pierre Raskin, V. Barral, 2016 .

$g_{m}/I_{\rm d}$ Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold

Denis Flandre, Tamara Rudenko, Valeria Kilchytska, 2010, IEEE Electron Device Letters.

On the gm/ID-based approaches for threshold voltage extraction in advanced MOSFETs and their application to ultra-thin body SOI MOSFETs

Denis Flandre, Jean-Pierre Raskin, Tamara Rudenko, 2014 .