O. Hinsinger

Post-Etch Cleaning Chemistries Evaluation for Low k-Copper Integration

P. Besson, L. Broussous, O. Hinsinger, 2003 .

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

C. Fenouillet-Béranger, R. Beneyton, J. Mazurier, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Reliability challenges accompanied with interconnect downscaling and ultra low-k dielectrics

R. Fox, R. Hoofman, J. Michelon, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..