T. Morooka

Physical understanding of the reliability improvement of dual high-k CMOSFETs with the fifth element incorporation into HfSiON gate dielectrics

Y. Ohji, S. Kamiyama, Y. Nara, 2008, 2008 Symposium on VLSI Technology.

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

K. Ohuchi, H. Ishiuchi, N. Aoki, 2005, 2005 IEEE International SOI Conference Proceedings.

Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method

Mitsumasa Koyanagi, Hiroyuki Kurino, Ki-Tae Park, 2001 .

Guideline for Low-temperature-operation Technique to Extend CMOS Scaling

Y. Toyoshima, K. Ohuchi, N. Aoki, 2006, 2006 International Electron Devices Meeting.

Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control

Y. Ohji, S. Kamiyama, Y. Nara, 2009, IEEE Transactions on Electron Devices.

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

K. Yahashi, N. Kusunoki, K. Ohuchi, 2006, 2006 European Solid-State Device Research Conference.

Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates

Y. Nara, K. Ohmori, T. Matsuki, 2008, 2008 IEEE International Electron Devices Meeting.