Nalesh Sivanandan

Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA

Babita R. Jose, Debdeep Paul, S. Kala, 2018, 2018 8th International Symposium on Embedded Computing and System Design (ISED).

UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs

Jimson Mathew, Babita R. Jose, B. R. Jose, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

Jimson Mathew, Marco Ottavi, Babita R. Jose, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2014, J. Syst. Archit..

Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture

S. K. Nandy, Ranjani Narayan, S. Kala, 2015, J. Low Power Electron..

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Compiling HPC Kernels for the REDEFINE CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

Energy aware synthesis of application kernels through composition of data-paths on a CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2017, Integr..

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

Jimson Mathew, Babita R. Jose, S. Kala, 2019, IET Comput. Digit. Tech..

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

S. K. Nandy, Ranjani Narayan, Farhad Merchant, 2015, 2015 28th International Conference on VLSI Design.

High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit

S. K. Nandy, Ranjani Narayan, S. Kala, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems

S. K. Nandy, Ranjani Narayan, S. Kala, 2014, 2014 Fifth International Symposium on Electronic System Design.

Efficient Hardware Acceleration of Convolutional Neural Networks

Jimson Mathew, Babita R. Jose, S. Kala, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).