Tetsuo Nakano

A 120-MHz BiCMOS superscalar RISC processor

Hirozi Yamada, Kotaro Shimamura, Shigeya Tanaka, 1994 .

3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

Takashi Hotta, Tetsuo Nakano, Kozaburo Kurita, 1990 .

BiCMOS Circuit Techniques for 3.3 V Microprocessors (Special Section on Low-Power and Low-Voltage Integrated Circuits)

Fumio Murabayashi, Tatsumi Yamauchi, Takashi Hotta, 1993 .

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

Fumio Murabayashi, Tatsumi Yamauchi, Hirozi Yamada, 1994 .

A semiconductor integrated circuit device with low power consumption and method for its operation

Shigeya Tanaka, Hideo Maejima, Masahiro Iwamura, 1990 .