Takahiro Watanabe

发表

Evolutionary design for image filter using GA

Zhiguo Bao, Takahiro Watanabe, Zhiguo Bao, 2009, TENCON 2009 - 2009 IEEE Region 10 Conference.

A-3-2 A Parallel Routing Method using Virtual Boundary

Takahiro Watanabe, Ran Zhang, Takahiro Watanabe, 2012 .

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

Takahiro Watanabe, Ran Zhang, Li Zhu, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device

Takahiro Watanabe, Li Zhu, Lian Zeng, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits

Takahiro Watanabe, Tadao Nakamura, Hiroyuki Matsubara, 2000 .

A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs

Takahiro Watanabe, Lian Zeng, Tieyuan Pan, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multi-Shape Task Placement Algorithm Based on Low Fragmentation Resource Management on 2D Heterogeneous Dynamic Partial Reconfigurable Devices

Tieyuan Pan, Takahiro Watanabe, Michael Conrad Meyer, 2020, IEEE Access.

Design of high-throughput SHA-256 hash function based on FPGA

Takahiro Watanabe, Shamsiah binti Suhaili, Takahiro Watanabe, 2017, 2017 6th International Conference on Electrical Engineering and Informatics (ICEEI).

An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Predicting stock high price using forecast error with recurrent neural network

Zhiguo Bao, Takahiro Watanabe, Tingyu Zhou, 2021, Applied Mathematics and Nonlinear Sciences.

High performance and low latency mapping for neural network into network on chip architecture

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2009, 2009 IEEE 8th International Conference on ASIC.

High dependable implementation of Neural Networks with networks on chip architecture and a backtracking routing algorithm

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2009, 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia).

DS-1-3 DESIGN AND IMPLEMENTATION OF SHA-1 HASH FUNCTION USING VERILOG HDL

Takahiro Watanabe, S. Suhaili, Takahiro Watanabe, 2012 .

A Fast Online Task Placement Algorithm for Three-Dimensional Dynamic Partial Reconfigurable Devices

Tieyuan Pan, Takahiro Watanabe, Michael Conrad Meyer, 2020, IEEE Access.

Fault-tolerant image filter design using particle swarm optimization

Takahiro Watanabe, Fangfang Wang, Xiaoming Zhao, 2011, Artificial Life and Robotics.

Region Oriented Routing FPGA Architecture for Dynamic Power Gating

Yiping Dong, Takahiro Watanabe, Ce Li, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

Yiping Dong, Takahiro Watanabe, Ce Li, 2012, IEICE Trans. Inf. Syst..

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

Yiping Dong, Takahiro Watanabe, Ce Li, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM

Yiping Dong, Takahiro Watanabe, Ce Li, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

New power-efficient FPGA design combining with region-constrained placement and multiple power domains

Yiping Dong, Takahiro Watanabe, Ce Li, 2011, 2011 IEEE 9th International New Circuits and systems conference.

RC-002 A Novel Low Power FPGA Architecture

Takahiro Watanabe, Yiping Done, Takahiro Watanabe, 2010 .

High performance Networks on Chip architecture with a new routing strategy for neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Multiple Network-on-Chip Model for High Performance Neural Network

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010 .

High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.