Y. Hsu

发表

LiB: a CMOS cell compiler

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Advanced techniques for RTL debugging

Yu-Chin Hsu, Yirng-An Chen, B. Tabbara, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Visibility enhancement for silicon debug

Yu-Chin Hsu, Fur-Shing Tsai, Ying-Tsai Chang, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

A new approach to schedule operations across nested-ifs and nested-loops

Yen-Jen Oyang, Shih-Hsu Huang, Yu-Chin Hsu, 1995, MICRO 25.

We 4 Experimental Results Technology: 0:5m Cmos Ic Multi-chip Modules (mcms)

T. C. Hu, B. A. McCoy, A. Kahng, 1995 .

Rectilinear Steiner tree construction by local and global refinement

Yu-Chin Hsu, Ting-Hai Chao, Y. Hsu, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Synthesis of false loop free circuits

Y. Oyang, Y. Hsu, Shih-Hsu Huang, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

A New Approach To Schedule Operations Across Nested-ifs And Nested-loops

Y. Oyang, Y. Hsu, Shih-Hsu Huang, 1992, [1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25.

Combining Logic Minimization and Folding for PLA's

Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, 1991, IEEE Trans. Computers.

Zero skew clock routing with minimum wirelength

Jan-Ming Ho, Andrew B. Kahng, Yu-Chin Hsu, 1992 .

PLS: a scheduler for pipeline synthesis

Yu-Chin Hsu, Youn-Long Lin, Cheng-Tsung Hwang, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Scheduling for functional pipelining and loop winding

Yu-Chin Hsu, Youn-Long Lin, Cheng-Tsung Hwang, 1991, 28th ACM/IEEE Design Automation Conference.

A formal approach to the scheduling problem in high level synthesis

Yu-Chin Hsu, Cheng-Tsung Hwang, Jiahn-Humg Lee, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cell height driven transistor sizing in a cell based module design

How-Rern Lin, Yu-Chin Hsu, TingTing Hwang, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Zero skew clock net routing

Jan-Ming Ho, Yu-Chin Hsu, Ting-Hai Chao, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

STAR: An automatic data path allocator

Yu-Chin Hsu, Fur-Shing Tsai, Y. Hsu, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Digital design from concept to prototype in hours

Yu-Chin Hsu, T. Y. Liu, F. S. Tsai, 1994, Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems.

Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

Yu-Chin Hsu, M. Fujita, Mike Tien-Chien Lee, 1996, 33rd Design Automation Conference Proceedings, 1996.

MULTIPAR: behavioral partition for synthesizing multiprocessor architectures

Chung-Ta King, Yu-Chin Hsu, Yunn Yen Chen, 1994, IEEE Trans. Very Large Scale Integr. Syst..

A Tree-Based Scheduling Algorithm for Control-Dominated Circuits

J. F. Wang, Y. C. Hsu, S. H. Huang, 1993, 30th ACM/IEEE Design Automation Conference.

Data path allocation based on bipartite weighted matching

Yu-Chin Hsu, Youn-Long Lin, Chu-Yi Huang, 1990, 27th ACM/IEEE Design Automation Conference.

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs

Yu-Chin Hsu, Fur-Shing Tsai, Chieh Changfan, 2002, TODE.

SILK: a simulated evolution router

Yu-Chin Hsu, Youn-Long Lin, Fur-Shing Tsai, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance

Frank Vahid, Yu-Chin Hsu, Thuy Dm Le, 1998, TODE.

A fast transistor-chaining algorithm for CMOS cell layout

Yu-Chin Hsu, Chi-Yi Hwang, Youn-Long Lin, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A detailed router based on simulated evolution

Yu-Chin Hsu, Youn-Long Lin, Fur-Shing Tsai, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Functional Partitioning for Low Power

F. Vahid, Y. Hsu, Yang-Chang Hong, 1999 .

A new integer linear programming formulation for the scheduling problem in data path synthesis

Youn-Long Lin, Yu-Chin Hsu, Jiahn-Hung Lee, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

LIP: a data path scheduler using linear integer programming

Yu-Chin Hsu, Youn-Long Lin, Jiahn-Hurng Lee, 1989, International Symposium on VLSI Technology, Systems and Applications,.

High throughput pipelined data path synthesis by conserving the regularity of nested loops

Yu-Chin Hsu, Jhing-Fa Wang, Yuan-Long Jeang, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Optimum and heuristic data path scheduling under resource constraints

Y. Lin, Y. Hsu, C. Hwang, 1990, 27th ACM/IEEE Design Automation Conference.

Hybrid routing

Yu-Chin Hsu, Youn-Long Lin, Fur-Shing Tsai, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..