Zhengfeng Huang

发表

Design of MNU-Resilient latches based on input-split C-elements

Zhengfeng Huang, Yiming Ouyang, Tianming Ni, 2021, Microelectron. J..

HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch

Zhengfeng Huang, Huaguo Liang, Hui Xu, 2021, Electronics.

Test data compression of system-on-chip (SoC) using few relevant bits: Test data compression of system-on-chip (SoC) using few relevant bits

Tao Xie, Huaguo Liang, Zhengfeng Huang, 2013 .

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

Huaguo Liang, Zhengfeng Huang, Yiming Ouyang, 2016, IEEE Transactions on Nuclear Science.

Fault-tolerant design of redundant bidirectional TSV on 3D NoC: Fault-tolerant design of redundant bidirectional TSV on 3D NoC

Tao Xie, Huaguo Liang, Zhengfeng Huang, 2014 .

A reconfigurable PUF structure with dual working modes based on entropy separation model

Zhengfeng Huang, Huaguo Liang, Yingchun Lu, 2022, Microelectronics Journal.

A highly reliable butterfly PUF in SRAM-based FPGAs

Huaguo Liang, Zhengfeng Huang, Yiming Ouyang, 2017, IEICE Electron. Express.

Rapid detection of trace Cu2+ using an l‐cysteine based interdigitated electrode sensor integrated with AC electrokinetic enrichment

Jayne Wu, Zhengfeng Huang, Huaguo Liang, 2019, Electrophoresis.

RLDA: Valid test pattern identification by machine learning classification method for VLSI test

Zhengfeng Huang, Tai Song, Xiaohui Guo, 2022, Microelectronics Journal.

Research on physical unclonable functions circuit based on three dimensional integrated circuit

Zhengfeng Huang, Hao Xiao, Tianming Ni, 2018, IEICE Electron. Express.

Valid Test Pattern Identification for VLSI Adaptive Test

Zhengfeng Huang, Tianming Ni, Ji Wan, 2021, 2021 China Semiconductor Technology International Conference (CSTIC).

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

Huaguo Liang, Tianming Ni, Zhengfeng Huang, 2020, IEEE Access.

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory

Ying Sun, Huaguo Liang, Zhengfeng Huang, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications

Patrick Girard, Zhengfeng Huang, Aibin Yan, 2020, IEEE Transactions on Aerospace and Electronic Systems.

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

Xiaoqing Wen, Zhengfeng Huang, Kang Yang, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Architecture of Cobweb-Based Redundant TSV for Clustered Faults

Huaguo Liang, Qi Xu, Tianming Ni, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Temperature-Aware Floorplanning for Fixed-Outline 3D ICs

Huaguo Liang, Zhengfeng Huang, Tianming Ni, 2019, IEEE Access.

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments

P. Girard, X. Wen, Zhengfeng Huang, 2023, IEEE Transactions on Aerospace and Electronic Systems.

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications

Patrick Girard, Xiaoqing Wen, Yan Chen, 2020, IEEE Transactions on Aerospace and Electronic Systems.

Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

P. Girard, X. Wen, Zhengfeng Huang, 2022, IEEE Transactions on Device and Materials Reliability.

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

P. Girard, Hao Zheng, X. Wen, 2022, IEEE Transactions on Aerospace and Electronic Systems.

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Zhili Chen, Zhengfeng Huang, Tianming Ni, 2022, IEEE Transactions on Emerging Topics in Computing.

CNN-based Monocular Decentralized SLAM on embedded FPGA

Yu Wang, Chao Yu, Huazhong Yang, 2020, 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

An improved communication scheme for non-HOL-blocking wireless NoC

Huaguo Liang, Zhengfeng Huang, Kun Xing, 2018, Integr..

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

Zhili Chen, Tianming Ni, Zhengfeng Huang, 2020, IEEE Transactions on Computers.

M-RO PUF: A portable pure digital RO PUF based on MUX unit

Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi, 2021, Microelectron. J..

LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS

Zhengfeng Huang, Tianming Ni, Huaguo Liang, 2021, Microelectron. J..

Balancing wrapper chains of SoC core based on best interchange decreasing

Huaguo Liang, Zhengfeng Huang, Maoxiang Yi, 2008, 2008 International Symposium on System-on-Chip.

Giant dielectric behavior in CaLaAlO4 ceramics

Jianan Zhang, C. C. Wang, Zhengfeng Huang, 2016 .

A Nanofluidic Sensor for Real-Time Detection of Ultratrace Contaminant Particles in IC Fabrication

Jiehong Wu, Zhengfeng Huang, Huaguo Liang, 2021, IEEE Sensors Journal.

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, 2016, Microelectron. Reliab..

Generalized Transfer Extreme Learning Machine for Unsupervised Cross-Domain Fault Diagnosis With Small and Imbalanced Samples

Aisong Qin, Xinxin Li, H. Mao, 2023, IEEE Sensors Journal.

A SLAM Pose Graph Optimization Method Using Dual Visual Odometry

Yu Wang, Zhengfeng Huang, Jincheng Yu, 2021 .

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells

Huaguo Liang, Xuejun Li, Zhengfeng Huang, 2019, 2019 IEEE International Test Conference in Asia (ITC-Asia).

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Lin Lu, Huaguo Liang, Tianming Ni, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fault tolerance in memristive crossbar-based neuromorphic computing systems

Hao Geng, Bei Yu, Bo Yuan, 2020, Integr..

GAME: Gaussian Mixture Model Mapping and Navigation Engine on Embedded FPGA

Yu Wang, Zhengfeng Huang, Jincheng Yu, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion

X. Wen, Zhengfeng Huang, Huaguo Liang, 2023, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology

Yang Zhao, Xiaoqing Wen, Zhengfeng Huang, 2021, IEEE Transactions on Emerging Topics in Computing.

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications

X. Wen, Zhengfeng Huang, Tianming Ni, 2022, Integr..

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Patrick Girard, Zhengfeng Huang, Jun Zhou, 2019, IEEE Access.

A Low-Cost and Robust Latch Protected against Triple Node Upsets in Nanoscale CMOS based on Source-Drain Cross-Coupled Inverters

X. Wen, Zhengfeng Huang, Aibin Yan, 2022, 2022 IEEE 22nd International Conference on Nanotechnology (NANO).

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Xiaoqing Wen, Zhengfeng Huang, Jing Guo, 2018, IEEE Transactions on Emerging Topics in Computing.

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

Huaguo Liang, Zhengfeng Huang, Yiming Ouyang, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A High Performance SEU Tolerant Latch

S. Hellebrand, Zhengfeng Huang, Huaguo Liang, 2015, J. Electron. Test..

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

Huaguo Liang, Tianming Ni, Zhengfeng Huang, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Highly Robust Double Node Upset Resilient Hardened Latch Design

Xin Li, Huaguo Liang, Zhengfeng Huang, 2017, IEICE Trans. Electron..

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS

Zhengfeng Huang, Yiming Ouyang, Honghui Deng, 2017, Microelectron. J..

High-performance, low-cost, and highly reliable radiation hardened latch design

Huaguo Liang, Cuiyun Jiang, Aibin Yan, 2016 .

Design of Low-Cost Approximate CMOS Full Adders

P. Girard, X. Wen, Zhengfeng Huang, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Huaguo Liang, Yang Guo, Zhengfeng Huang, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

P. Girard, X. Wen, Zhengfeng Huang, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator

Zhengfeng Huang, Tianming Ni, Maoxiang Yi, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

Jitter-Quantizing-Based TRNG Robust Against PVT Variations

Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, 2020, IEEE Access.

NBTI mitigation by M-IVC with input duty cycle and randomness constraints

Huaguo Liang, Zhengfeng Huang, Xiaohong Liu, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).