C. H. Hsieh

Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

Shien-Yang Wu, T. Miyashita, C. H. Tsai, 2016, 2016 IEEE Symposium on VLSI Technology.

NBTI improvement for pMOS by Cl-contained 1st oxidation in 20A/65A dual-nitrided gate oxide of 0.13-μm CMOS technology

Min-Hwa Chi, Chih-Hsiung Lee, Chao-Chi Chen, 2003, SPIE Advanced Lithography.

COLOUR DEVIATION SENSING AND COMPENSATION METHOD FOR MULTI-SPECTRAL LED LIGHTING SYSTEM

C. H. Hsieh, Z. W. Wang, H. K. Fu, 2018 .

Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-μm CMOS technology

H. J. Liao, Chih-Hao Chang, C. H. Hsieh, 2003, SPIE Advanced Lithography.

A new enhancement layer to improve copper interconnect performance

C. H. Hsieh, H. J. Tao, S. M. Jeng, 2010, 2010 IEEE International Interconnect Technology Conference.