G. Groeseneken

发表

Novel architecture to boost the vertical tunneling in Tunnel Field Effect Transistors

A. Vandooren, D. Leonelli, R. Rooyackers, 2011, IEEE 2011 International SOI Conference.

Challenges in Reliability Assessment of Advanced CMOS Technologies

G. Groeseneken, R. Degraeve, B. Kaczer, 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Hot carrier aging and its variation under use-bias: Kinetics, prediction, impact on Vdd and SRAM

A. Asenov, G. Groeseneken, B. Kaczer, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation—Application to 6T SRAM

G. Groeseneken, B. Kaczer, P. Weckx, 2014, 2014 IEEE International Reliability Physics Symposium.

On the rseries extraction techniques for sub-22nm CMOS finfet and SiGe technologies

G. Groeseneken, Luigi Pantisano, G. Hellings, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Modeling and simulation for ESD protection circuit design and optimization

G. Groeseneken, V. Vassilev, N.M. Iyer, 2004, 2004 IEEE International Conference on Semiconductor Electronics.

Comparative study of hot-carrier degradation in p+ and n+ poly p-MOSFET's of a 0.5 μm CMOS technology

G. Groeseneken, C. Monserie, H. E. Maes, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

Time and workload dependent device variability in circuit simulations

G. Groeseneken, D. Soudris, B. Kaczer, 2011, 2011 IEEE International Conference on IC Design & Technology.

Physically unclonable function using CMOS breakdown position

G. Groeseneken, R. Degraeve, B. Kaczer, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Deterministic and field-free voltage-controlled MRAM for high performance and low power applications

G. Groeseneken, J. Van Houdt, Y. C. Wu, 2020, 2020 IEEE Symposium on VLSI Technology.

Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits

G. Groeseneken, J. Mitard, F. Crupi, 2013, IEEE Transactions on Electron Devices.

Class 3 HBM and class M4 MM ESD protected 5.5 GHz LNA in 90 nm RFCMOS using above-IC inductor

P. Soussan, P. Wambacq, G. Groeseneken, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

CDM and HBM analysis of ESD protected 60 GHz power amplifier in 45 nm low-power digital CMOS

G. Groeseneken, D. Linten, K. Raczkowski, 2009, 2009 31st EOS/ESD Symposium.

A fully-integrated method for RTN parameter extraction

P. Wambacq, B. Parvais, G. Groeseneken, 2017, 2017 Symposium on VLSI Technology.

Time-dependent variation: A new defect-based prediction methodology

A. Asenov, G. Groeseneken, B. Kaczer, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

TDDB Reliability Prediction Based on the Statistical Analysis of Hard Breakdown Including Multiple Soft Breakdown and Wear-out

G. Groeseneken, R. Degraeve, B. Kaczer, 2007, 2007 IEEE International Electron Devices Meeting.

ESD diodes in a bulk Si gate-all-around vertically stacked horizontal nanowire technology

G. Groeseneken, G. Hellings, D. Linten, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

The High Injection MOS cell: a novel 5V-only Flash EEPROM concept with a 1 μs programming time

G. Groeseneken, L. Deferm, D. Wellekens, 1991, ESSDERC '91: 21st European Solid State Device Research Conference.

Advanced MOSFET variability and reliability characterization array

B. Parvais, G. Groeseneken, G. Gielen, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

Calibration of very fast TLP transients

G. Groeseneken, M. Sawada, P. Roussel, 2009, 2009 31st EOS/ESD Symposium.

Modeling RRAM set/reset statistics resulting in guidelines for optimized operation

G. Groeseneken, R. Degraeve, L. Goux, 2013, 2013 Symposium on VLSI Technology.

From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation

G. Groeseneken, B. Kaczer, J. Franco, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Characterization and modeling of diodes in Sub-45 nm CMOS technologies under HBM stress conditions

G. Groeseneken, M. Sawada, D. Linten, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Improving the ESD self-protection capability of integrated power NLDMOS arrays

G. Groeseneken, D. Linten, S. Thijs, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

Characterization and modeling of transient device behavior under CDM ESD stress

G. Groeseneken, H. Gieser, M. Etherton, 2004, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

G. Groeseneken, M. Steyaert, V. Vassilev, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Origin of wide retention distribution in 1T Floating Body RAM

G. Groeseneken, E. Simoen, C. Claeys, 2012, 2012 IEEE International SOI Conference (SOI).

Statistical assessment of the full VG/VD degradation space using dedicated device arrays

G. Groeseneken, B. Kaczer, P. Weckx, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Subthreshold Source-Side Injection (S3I): A Promising Programming Mechanism for Scaled-Down, Low-Power Flash Memories

G. Groeseneken, L. Haspeslagh, L. Deferm, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

ESD protection for wideband RF CMOS LNAs

G. Groeseneken, D. Linten, S. Thijs, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Comparison Of The Suitability Of Various Programming Mechanisms Used For Multilevel Non-Volatile Information Storage

G. Groeseneken, D. Wellekens, J. Van Houdt, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

Atomistic approach to variability of bias-temperature instability in circuit simulations

G. Groeseneken, B. Kaczer, T. Grasser, 2011, 2011 International Reliability Physics Symposium.

Calibrated wafer-level HBM measurements for quasi-static and transient device analysis

G. Groeseneken, M. Sawada, D. Linten, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Circuit Design-Oriented Stochastic Piecewise Modeling of the Postbreakdown Gate Current in MOSFETs: Application to Ring Oscillators

G. Groeseneken, R. Degraeve, B. Kaczer, 2012, IEEE Transactions on Device and Materials Reliability.

Hot carrier degradation and ESD in submicron CMOS technologies: how do they interact?

G. Groeseneken, G. Groeseneken, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

Unexpected failure during HBM ESD stress in nanometer-scale nLDMOS-SCR devices

G. Groeseneken, D. Linten, S. Thijs, 2011, 2011 International Electron Devices Meeting.

Center balanced distributed ESD protection for 1–110 GHz distributed amplifier in 45 nm CMOS technology

G. Groeseneken, D. Linten, S. Thijs, 2009, 2009 31st EOS/ESD Symposium.

New understanding of dielectric breakdown in advanced FinFET devices — physical, electrical, statistical and multiphysics study

G. Groeseneken, D. Linten, N. Horiguchi, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Impact of elevated source drain architecture on ESD protection devices for a 90nm CMOS technology node

R. Rooyackers, G. Groeseneken, V. Vassilev, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

G. Groeseneken, K. De Meyer, A. S. Verhulst, 2013, IEEE Transactions on Electron Devices.

ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions

P. Wambacq, G. Groeseneken, R. Degraeve, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Design methodology of FinFET devices that meet IC-Level HBM ESD targets

R. Rooyackers, G. Groeseneken, M. Sawada, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

G. Groeseneken, E. Simoen, P. Blomme, 2012, IEEE Transactions on Electron Devices.

On the geometric component of charge-pumping current in MOSFETs

G. Groeseneken, H.E. Maes, G. Van den Bosch, 1993, IEEE Electron Device Letters.

ESD in FinFET technologies: Past learning and emerging challenges

G. Groeseneken, Shih-Hung Chen, G. Hellings, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Recent trends in reliability assessment of advanced CMOS technologies

G. Groeseneken, R. Degraeve, B. Kaczer, 2005, Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..

Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate

G. Groeseneken, G. Hellings, D. Linten, 2014, 2014 IEEE International Reliability Physics Symposium.

Perspectives of (sub-) 32nm CMOS for Analog/RF and mm-wave Applications

B. Parvais, G. Groeseneken, W. Sansen, 2008, 2008 European Microwave Integrated Circuit Conference.

A compact model for the grounded-gate nMOS behaviour under CDM ESD stress

G. Groeseneken, H. E. Maes, C. Russ, 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

A single device based voltage step stress (VSS) technique for fast reliability screening

S. De Gendt, G. Groeseneken, B. Kaczer, 2014, 2014 IEEE International Reliability Physics Symposium.

Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors

G. Groeseneken, S. You, X. Li, 2019, ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC).

An equivalent circuit model for the recovery component of BTI

G. Groeseneken, B. Kaczer, J. Martin-Martinez, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Interaction between hot carrier aging and PBTI degradation in nMOSFETs: Characterization, modelling and lifetime prediction

G. Groeseneken, B. Kaczer, A. Asenov, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Optimization of a submicron HIMOS Flash E2PROM cell for implementation in a virtual ground array configuration

G. Groeseneken, L. Haspeslagh, L. Deferm, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

Enhanced ESD protection robustness of a lateral NPN structure in the advanced CMOS

G. Groeseneken, V. Vassilev, M. Steyaert, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Key issues and techniques for characterizing time-dependent device-to-device variation of SRAM

A. Asenov, G. Groeseneken, B. Kaczer, 2013, 2013 IEEE International Electron Devices Meeting.

Multilevel Transmission Line Pulse (MTLP) tester

G. Groeseneken, V. Vassilev, S. Thijs, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Multi-level charge storage in source-side injection flash EEPROM

G. Groeseneken, L. Haspeslagh, L. Deferm, 1996, Proceedings of Nonvolatile Memory Technology Conference.

Statistical investigation of the impact of program history and oxide-metal interface on OxRRAM retention

G. Groeseneken, R. Degraeve, L. Goux, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology

P. Wambacq, G. Groeseneken, J. Borremans, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Investigation of the soft-write mechanism in source-side injection flash EEPROM devices

G. Groeseneken, D. Wellekens, H.E. Maes, 1995, IEEE Electron Device Letters.

On-wafer human metal model measurements for system-level ESD analysis

G. Groeseneken, M. Sawada, D. Linten, 2009, 2009 31st EOS/ESD Symposium.

Circuit-design oriented modelling of the recovery BTI component and post-BD gate currents

G. Groeseneken, B. Kaczer, B. Dierickx, 2009, 2009 Spanish Conference on Electron Devices.

Experimental calibration of the temperature dependence of the heterojunction bandgap in III-V tunneling devices

G. Groeseneken, A. S. Verhulst, Q. Smets, 2019, 2019 Device Research Conference (DRC).

Comparison of System-Level ESD Design Methodologies—Towards the Efficient and ESD Robust Design of Systems

G. Groeseneken, Shih-Hung Chen, M. Sawada, 2013, IEEE Transactions on Device and Materials Reliability.

On-chip circuit for massively parallel BTI characterization

G. Groeseneken, B. Kaczer, G. Van der Plas, 2011, 2011 IEEE International Integrated Reliability Workshop Final Report.

Potential vulnerability of dynamic CMOS logic to soft gate oxide breakdown

G. Groeseneken, B. Kaczer, B. Kaczer, 2003, IEEE Electron Device Letters.

Defect-centric perspective of combined BTI and RTN time-dependent variability

G. Groeseneken, B. Kaczer, P. Weckx, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

Tunnel FETs using Phosphorene/ReS2 heterostructures

G. Groeseneken, D. Lin, I. Radu, 2019, 2019 Device Research Conference (DRC).

Co-design methodology to provide high ESD protection levels in the advanced RF circuits

P. Wambacq, G. Groeseneken, M. Steyaert, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

A New TDDB Reliability Prediction Methodology Accounting for Multiple SBD and Wear Out

G. Groeseneken, R. Degraeve, B. Kaczer, 2009, IEEE Transactions on Electron Devices.

Mixed-mode simulations for power-on ESD analysis

G. Groeseneken, M. Sawada, D. Linten, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Turn-off characteristics of the CMOS snapback ESD protection devices - new insights and its implications

G. Groeseneken, V.A. Vashchenko, M. Sawada, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

Miscorrelation between IEC61000-4-2 type of HMM tester and 50 Ω HMM tester

G. Groeseneken, M. Sawada, G. Hellings, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Investigation and Suppression of the Gate Disturb Effect in Source-Side Injection Flash EEPROM Arrays

G. Groeseneken, L. Haspeslagh, L. Deferm, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

A test-proven As-grown-Generation (A-G) model for predicting NBTI under use-bias

S. De Gendt, G. Groeseneken, B. Kaczer, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A 4.5 kV HBM, 300 V CDM, 1.2 kV HMM ESD protected DC-to-16.1 GHz wideband LNA in 90 nm CMOS

G. Groeseneken, M. Okushima, J. Borremans, 2009, 2009 31st EOS/ESD Symposium.

Contributions to standardization of Transmission Line Pulse testing methodology

G. Groeseneken, B. Keppens, V. De Heyn, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

Self-protection capability of power arrays

G. Groeseneken, M. Sawada, D. Linten, 2009, 2009 31st EOS/ESD Symposium.

Semi-empirical interconnect resistance model for advanced technology nodes: A model apt for materials selection based upon test line resistance measurements

G. Groeseneken, R. Degraeve, D. Linten, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Trends in Non-Volatile Memory Devices and Technologies

G. Groeseneken, H.E. Maes, J. Writters, 1987, ESSDERC '87: 17th European Solid State Device Research Conference.

Negative bias temperature instability lifetime prediction: Problems and solutions

S. De Gendt, G. Groeseneken, B. Kaczer, 2013, 2013 IEEE International Electron Devices Meeting.

(Late) Reliability and performance considerations for NMOSFET pass gates in FPGA applications

G. Groeseneken, B. Kaczer, T. Grasser, 2013, 2013 IEEE International Integrated Reliability Workshop Final Report.

Maximizing reliable performance of advanced CMOS circuits—A case study

G. Groeseneken, B. Kaczer, T. Grasser, 2014, 2014 IEEE International Reliability Physics Symposium.