Ashoke Ravi

发表

MIMO techniques for high data rate radio communications

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

Yorgos Palaskas, Ashoke Ravi, Hongtao Xu, 2011, IEEE Journal of Solid-State Circuits.

A 2.5GHz delay-based wideband OFDM outphasing modulator in 45nm-LP CMOS

Marian Verhelst, Yorgos Palaskas, Ashoke Ravi, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET

Yorgos Palaskas, Ashoke Ravi, Petra Schubert, 2020, IEEE Journal of Solid-State Circuits.

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS

Michael P. Flynn, Yorgos Palaskas, Ashoke Ravi, 2006, IEEE Custom Integrated Circuits Conference 2006.

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS

Marian Verhelst, Yorgos Palaskas, Ashoke Ravi, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 90-nm MOS-only 3-11GHz transmitter for UWB

Yorgos Palaskas, Ashoke Ravi, Krishnamurthy Soumyanath, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Chapter 6 – Linear power amplification with high back-off efficiency: An out-phasing approach

Ashoke Ravi, Wei Tai, Hongtao Xu, 2016 .

A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS

Hyung Seok Kim, Ashoke Ravi, Krishnamurthy Soumyanath, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2012, 2012 IEEE International Solid-State Circuits Conference.

8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3/sup rd/ order, 3/5-bit IIR and 3/sup rd/ order 3-bit-FIR noise shapers in 90nm CMOS

Ashoke Ravi, Krishnamurthy Soumyanath, L. R. Carley, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

Calibration of a segmented digital-time converter

Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, 2015 .

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

Marian Verhelst, Hyung Seok Kim, Satoshi Suzuki, 2013, IEEE Journal of Solid-State Circuits.

A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O

Hyung Seok Kim, Ashoke Ravi, Kailash Chandrashekar, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation

Jeffrey S. Walling, Yorgos Palaskas, Ashoke Ravi, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 5-GHz 108-Mb/s 2x2 MIMO transceiver RFIC with fully integrated 20.5-dBm P1dB power amplifiers in 90-nm CMOS

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2006 .

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

Yorgos Palaskas, Ashoke Ravi, Krishnamurthy Soumyanath, 2010, 2010 Proceedings of ESSCIRC.

Linear power amplification with high back-off efficiency

Ashoke Ravi, Hongtao Xu, Wei Tai, 2016 .

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

Ashoke Ravi, Doris Schmitt-Landsiedel, Sebastian Sievert, 2016, IEEE Journal of Solid-State Circuits.

10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications

Ashoke Ravi, Rotem Banin, Anna Nazimov, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

Ashoke Ravi, Doris Schmitt-Landsiedel, Sebastian Sievert, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2012, IEEE Journal of Solid-State Circuits.

A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

Ashoke Ravi, Ofir Degani, Rotem Banin, 2020, IEEE Journal of Solid-State Circuits.

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement

Yorgos Palaskas, Ashoke Ravi, L. Richard Carley, 2012, IEEE Journal of Solid-State Circuits.

A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC

Hyung Seok Kim, Ashoke Ravi, Yee William Li, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

802.11g/n Compliant Fully Integrated Wake-Up Receiver With −72-dBm Sensitivity in 14-nm FinFET CMOS

Ashoke Ravi, Stefano Pellerano, Richard Dorrance, 2018, IEEE Journal of Solid-State Circuits.

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

Hyung Seok Kim, Satoshi Suzuki, Yorgos Palaskas, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Wi-Fi RF energy harvesting for battery-free wearable radio platforms

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2015, 2015 IEEE International Conference on RFID (RFID).

A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET

Ashoke Ravi, Borivoje Nikolic, Farhana Sheikh, 2018, 2018 IEEE Symposium on VLSI Circuits.

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS

Joy Laskar, Yorgos Palaskas, Ashoke Ravi, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications

Hyung Seok Kim, Satoshi Suzuki, Yorgos Palaskas, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

Hyung Seok Kim, Ashoke Ravi, Yee William Li, 2013, IEEE Journal of Solid-State Circuits.

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2010, IEEE Journal of Solid-State Circuits.

4 Design Considerations for Integrated MIMO Radio Transceivers

Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, 2007 .

95µW 802.11g/n compliant fully-integrated wake-up receiver with −72dBm sensitivity in 14nm FinFET CMOS

Ashoke Ravi, Stefano Pellerano, Jeffrey R. Foerster, 2017, 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

An integrated 10/5GHz injection–locked quadrature LC VCO in a 0.18µm digital CMOS process

Ashoke Ravi, Krishnamurthy Soumyanath, L. R. Carley, 2002 .

A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control

Yorgos Palaskas, Ashoke Ravi, L. Richard Carley, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

Ashoke Ravi, Kamran Azadet, Nir Geron, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).