Nozomu Togawa

发表

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Implementation evaluation of scan-based attack against a Trivium cipher circuit

Masao Yanagisawa, Nozomu Togawa, Daisuke Oku, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs

Masao Yanagisawa, Nozomu Togawa, Koichi Fujiwara, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1999 .

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures

Masao Yanagisawa, Nozomu Togawa, Kento Hasegawa, 2020, IEICE Trans. Inf. Syst..

Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine

Hidetoshi Matsuoka, Nozomu Togawa, Kazushi Kawamura, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

C-5 A Software/Hardware Codesign for MPEG Encoder

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests

Masao Yanagisawa, Kazuaki Ishikawa, Nozomu Togawa, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Capacitance Measurement Device for Running Hardware Devices and Its Evaluations

Nozomu Togawa, Kento Hasegawa, Makoto Nishizawa, 2020, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Hardware/Software Cosynthesis Method for CAM Processor with Area Constraints

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2020, IPSJ Trans. Syst. LSI Des. Methodol..

A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations

Masao Yanagisawa, Nozomu Togawa, Yuta Hagio, 2013 .

A thread partitioning algorithm in low power high-level synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal

Masao Yanagisawa, Tomoyuki Nitta, Nozomu Togawa, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2020, 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS).

A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

Masao Yanagisawa, Nozomu Togawa, Takashi Sakurai, 2001 .

Personalized Landmark Recommendation for Language-Specific Users by Open Data Mining

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2018 .

A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)

Tatsuo Ohtsuki, Nozomu Togawa, Masao Sato, 1996 .

A High - level Synthesis Algorithm with Floorplaning for a Distributed - register Architecture

Masao Yanagisawa, Akira Tanaka, Tatsuo Ohtsuki, 2004 .

An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications(Special Section on Discrete Mathematics and Its Applications)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

Simulation-Based Bus Width Optimization for Two-Level Caches

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

Indoor navigation based on real-time direction information generation using wearable glasses

Masao Yanagisawa, Tomoyuki Nitta, Kazuaki Ishikawa, 2016, 2016 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia).

How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

Nozomu Togawa, Daisuke Oku, Masashi Tawada, 2020, IEEE Transactions on Computers.

of a Fast Intra Prediction Algorithm for H.264/ A VC Encoding

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2010 .

A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

Floorplan-aware High-Level Synthesis for Distributed/Shared-Register Architectures

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2007 .

A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs (Special Section on VLSI Design and CAD Algorithms)

Tatsuo Ohtsuki, Nozomu Togawa, Masao Sato, 1997 .

Instruction set and functional unit synthesis for SIMD processor cores

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function

Nozomu Togawa, Masashi Tawada, 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS).

Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

High-level area/delay/power estimation for low power system VLSIs with gated clocks

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines

Nozomu Togawa, Junya Arai, Masashi Tawada, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

Fast Module Placement in Floorplan-aware High-level Synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines

Nozomu Togawa, Daisuke Oku, Shu Tanaka, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines

Nozomu Togawa, Masashi Tawada, Shu Tanaka, 2020, 2020 IEEE International Conference on Consumer Electronics (ICCE).

A Hardware Engine for Generation Deformed Map

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2007 .

An Area/Delay Estimation Technique for Control - Based Hardware Synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2001 .

A Fast Interpolation Unit Using Selector Logics

Nozomu Togawa, Manami Iwata, Hiromine Yoshihara, 2012 .

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

Personalized Landmark Recommendation Algorithm Based on Language-specific Satisfaction Prediction Using Heterogeneous Open Data Sources

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2018, 2018 10th International Conference on Computational Intelligence and Communication Networks (CICN).

Scan Vulnerability in Elliptic Curve Cryptosystems (IPSJ Transactions on System LSI Design Methodology Vol.4)

Masao Yanagisawa, Nozomu Togawa, Ryuta Nara, 2011 .

Two-level Cache Simulation with L2 Unified Cache for Embedded Applications

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

Consideration of A Bluetooth Network Scheme in Public Area based on Reducing a Hand-off Time

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2019, ICIS.

A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

FPGA-Based Reconfigurable Adaptive FEC

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A Floorplan-driven High-Level Synthesis Algorithm for Reducing Multiplexer Inputs Targeting FPGAs

Masao Yanagisawa, Nozomu Togawa, Koichi Fujiwara, 2014 .

FPGA-based Heterogeneous Solver for Three-Dimensional Routing

Nozomu Togawa, Kazushi Kawamura, Kento Hasegawa, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

High-level power optimization based on thread partitioning

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Energy Consumption Evaluation for Two-Level Cache with Non-Volatile Memory Targeting Mobile Processors

Masao Yanagisawa, Nozomu Togawa, Shinji Kimura, 2013 .

A Behavioral Synthesis System for Extended CAM Processors

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

Fast Scheduling and Allocation Algorithms for Entropy CODEC (Special Issue on Synthesis and Verification of Hardware Design)

Tatsuo Ohtsuki, Nozomu Togawa, Masao Sato, 1997 .

Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board

Nozomu Togawa, Kazushi Kawamura, Kento Hasegawa, 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

A hardware/software cosynthesis system for digital signal processor cores with two types of register files

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1999 .

Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis

Nozomu Togawa, Kento Hasegawa, Kiyoshi Chikamatsu, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A Hardware/Software Partitioning Framework for SIMD Processor Cores

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2007 .

A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration (Special Section on VLSI Design and CAD Algorithms)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

A BGA Package Routing Algorithm on Sketch Layout System

Tatsuo Ohtsuki, Nozomu Togawa, Masao Sato, 1997 .

A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)

Tatsuo Ohtsuki, Nozomu Togawa, Masao Sato, 1997 .

FPGA Design and Evaluation of Volume Rendering Circuits Using Selector Logic

Nozomu Togawa, Yanagisawa Masao, Igarashi Keita, 2016 .

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A Control/Data Flow Graph Transformation Algorithm in High-Level Synthesis for Control-Based Hardwares

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A Hardware/Software Cosynthesis System for Processors with Content Addressable Memory

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Masao Yanagisawa, Nozomu Togawa, Kotaro Terada, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A Hardware/Software Partitioning Algorhithm for Image Processors with a Packed SIMD Type Instruction Set

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A-6-5 Evaluation of A Floorplan-aware High-level Synthesis Algorithm Optimizing Critical Path for FPGA Designs

Masao Yanagisawa, Nozomu Togawa, Kazushi Kawamura, 2016 .

System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed-Register Architectures

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2008 .

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tatsuo Ohtsuki, Nozomu Togawa, Masashi Tawada, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs

Youhua Shi, Masao Yanagisawa, Nozomu Togawa, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation

Masao Yanagisawa, Nozomu Togawa, Kazushi Kawamura, 2012 .

Document-Level Sentiment Classification in Japanese by Stem-Based Segmentation with Category and Data-Source Information

Nozomu Togawa, Siya Bao, 2020, 2020 IEEE 14th International Conference on Semantic Computing (ICSC).

CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2000 .

An Area/Delay Estimation Method for an Application Processor in HW/SW Cosynthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2006 .

A Route Recommendation Method Based on Personal Preferences by Monte-Carlo Tree Search

Nozomu Togawa, Toshinori Takayama, Yuta Ishizaki, 2019, 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin).

From the EDA perspective

Nozomu Togawa, 2016 .

A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems

Masao Yanagisawa, Masayoshi Tachibana, Tatsuo Ohtsuki, 2009 .

Theory of Ising Machines and a Common Software Platform for Ising Machines

Nozomu Togawa, Shu Tanaka, Yoshiki Matsuda, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

System-level Function and Architecture Codesign for Optimization of MPEG Encoder

Tatsuo Ohtsuki, Nozomu Togawa, Jinku Choi, 2002 .

Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines

Nozomu Togawa, Shu Tanaka, Tatsuhiko Shirai, 2020, IEEE Access.

Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists

Nozomu Togawa, Seira Hidano, Shinsaku Kiyomoto, 2019, CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS.

Error Correction Coding of Stochastic Numbers Using BER Measurement

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).