R. Turner

Hierarchical DSP architectural synthesis and scheduling solution for "IRIS"

Roger Woods, Ying Yi, R. Turner, 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

A Parameterisable Motion Estimation Core

Roger Woods, R. Turner, E. LeRiguer, 2003 .

FPGA-based Implementation of Signal Processing Systems

Roger Woods, Gaye Lightbody, John McAllister, 2017 .

A virtual hardware handler for run-time reconfiguration systems

Roger Woods, Sakir Sezer, R. Turner, 1999 .

Low-power systolic array processor architecture for FSBM video motion estimation

Danny Crookes, R. Turner, Stuart Davidson, 2006 .