Kobayashi Kazutoshi

发表

Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes.

Sonezaki Eiji, Kanto Kubota, Masuda Masaki, 2015 .

Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System

Furuta Jun, Kobayashi Kazutoshi, Umehara Shigehiro, 2016 .

Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing

Matsumoto Takashi, Onodera Hidetoshi, Kobayashi Kazutoshi, 2011 .

Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield

Onodera Hidetoshi, Kobayashi Kazutoshi, Sugihara Yuuri, 2007 .

Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process

Kishida Ryo, Onodera Hidetoshi, Kaczer Ben, 2016 .

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology

Amano Hideharu, Okanishi Shinobu, Yanagita Hiroshi, 2014 .

Endurance Measurement of Semiconductor Chips-Beam Test by Particle Accelerator for Single Event Effects-

Kobayashi Kazutoshi, 2017 .

Reliability on Integrated Circuits -- Details of Soft Errors

Kobayashi Kazutoshi, 2014 .

Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations

Furuta Jun, Kobayashi Kazutoshi, Umehara Shigehiro, 2016 .

Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA

Kobayashi Kazutoshi, Yabuuchi Michitarou, 2014 .

A 65nm CMOS High-Speed and High-Fidelity NBTI Recovery Sensor

Onodera Hidetoshi, Kobayashi Kazutoshi, Matsumoto Takashi, 2010 .

Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect

Onodera Hidetoshi, Kobayashi Kazutoshi, Yuyama Yoichi, 2005 .

Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay

Onodera Hidetoshi, Kobayashi Kazutoshi, Matsumoto Takashi, 2014 .

Reliability on Integrated Circuits

Kobayashi Kazutoshi, 2015 .

Ringing Suppression of Wiring Inductance by the RCD Snubber for MHz-Switching of SiC-MOSFET

Furuta Jun, Kobayashi Kazutoshi, Yamashita Yuki, 2017 .

How to Mitigate Reliability-related Issues on Nano-scaled LSIs

Kobayashi Kazutoshi, Kobayashi Kazutoshi, 2012 .

Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values

Yao Jun, Shimada Hajime, Masuda Masaki, 2013 .

Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation

Onodera Hidetoshi, Kobayashi Kazutoshi, Matsumoto Takashi, 2012 .

Speed enhancement of FPGAs by reconfigration utilizing variations within a chip

Onodera Hidetoshi, Kobayashi Kazutoshi, Ogata Kosuke, 2006 .

A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop

Onodera Hidetoshi, Masuda Masaki, Furuta Jun, 2012 .

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element

Onodera Hidetoshi, Furuta Jun, Kobayashi Kazutoshi, 2010 .