Ming-Hsien Tu

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Chien-Yu Lu, Ming-Chien Tsai, Ming-Hsien Tu, 2012, IEEE Journal of Solid-State Circuits.

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Chien Tsai, Ming-Hsien Tu, Shyh-Jye Jou, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.