R. Ramanarayanan

Split-Path Fused Floating Point Multiply Accumulate (FPMAC)

Sanu Mathew, Ram Krishnamurthy, Tiju Jacob, 2013, 2013 IEEE 21st Symposium on Computer Arithmetic.

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors

Mahmut T. Kandemir, Guilin Chen, Liping Xue, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).