C. Faulkner

Fermi-level depinning for low-barrier Schottky source/drain transistors

Daniel J. Connelly, D. Connelly, P. Clifton, 2006 .

Plasma etch technologies for the development of ultra-small feature size transistor devices

Justin D. Holmes, Richard A. Farrell, Michael A. Morris, 2011 .

A new route to zero-barrier metal source/drain MOSFETs

C. Faulkner, J.S. Harris, D. Connelly, 2004, IEEE Transactions on Nanotechnology.

Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

C. Faulkner, D. Connelly, D. Grupp, 2003, IEEE Electron Device Letters.

Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS

C. Faulkner, Daniel J. Connelly, D. Connelly, 2003 .