Kwen-Siong Chong

发表

A power-efficient integrated input/output completion detection circuit for asynchronous-logic quasi-delay-insensitive Pre-Charged Half-Buffer

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2011, 2011 International Symposium on Integrated Circuits.

Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2020, ISCAS.

A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2012, IEEE Journal of Solid-State Circuits.

A micropower low-voltage multiplier with reduced spurious switching

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2019, IEEE Transactions on Information Forensics and Security.

Ultra low-power filter bank for hearing aid speech processor

Kwen-Siong Chong, P. Mazumder, M. Barangi, 2012, 2012 IEEE Subthreshold Microelectronics Conference (SubVT).

Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things

Kwen-Siong Chong, Joseph Sylvester Chang, Jize Jiang, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

A robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling system

Wei Shu, Kwen-Siong Chong, Bah-Hwee Gwee, 2012, 2012 IEEE Subthreshold Microelectronics Conference (SubVT).

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

Kwen-Siong Chong, Bah-Hwee Gwee, Junchao Chen, 2014, Circuits Syst. Signal Process..

Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design

Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques

Kwen-Siong Chong, Pinaki Mazumder, Joseph Sylvester Chang, 2012, 2012 International Symposium on Electronic System Design (ISED).

Single-Event-Transient Resilient Memory for DSP in Space Applications

Kwen-Siong Chong, Joseph Sylvester Chang, Ne Kyaw Zwa Lwin, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

Highly secured state-shift local clock circuit to countermeasure against side channel attack

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of several asynchronous-logic macrocells for a low-voltage micropower cell library

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2007, IET Circuits Devices Syst..

A low-power dual-rail inputs write method for bit-interleaved memory cells

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Title Energy-efficient synchronous-logic and asynchronous- logic FFT/IFFT processors( Published )

Kwen-Siong Chong, Joseph Chang, Bah Hwee, 2007 .

A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES)

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2020, ISCAS.

Synthesis of asynchronous QDI circuits using synchronous coding specifications

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Low Energy FFT/IFFT Processor for Hearing Aids

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2007, 2007 IEEE International Symposium on Circuits and Systems.

An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive $V_{\rm DD}$ System for Wireless Sensor Networks

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2013, IEEE Journal of Solid-State Circuits.

Low-voltage asynchronous adders for low power and high speed applications

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Highly secured arithmetic hiding based S-Box on AES-128 implementation

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2016, 2016 International Symposium on Integrated Circuits (ISIC).

Success rate model for fully AES-128 in correlation power analysis

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2009, 2009 IEEE International Symposium on Circuits and Systems.

DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS

Kwen-Siong Chong, Pinaki Mazumder, Joseph Sylvester Chang, 2013, GLSVLSI '13.

A robust low voltage low energy asynchronous carry-completion sensing adder for biomedical applications

Kwen-Siong Chong, Bah-Hwee Gwee, J.S. Chang, 2004, IEEE International Workshop on Biomedical Circuits and Systems, 2004..

A Simple Methodology of Designing Asynchronous Circuits Using Commercial IC Design Tools and Standard Library Cells

Kwen-Siong Chong, Bah-Hwee Gwee, J.S. Chang, 2007, 2007 International Symposium on Integrated Circuits.

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM

Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A Secure Data-Toggling SRAM for Confidential Data Protection

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process

Wei Shu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process

Kwen-Siong Chong, Joseph Sylvester Chang, Ne Kyaw Zwa Lwin, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications

Ali Akbar Pammu, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).

An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Asynchronous circuits for dynamic voltage scaling

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2019 .

Synthesis of Asynchronous Circuits from Verilog Specifications

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, 2011 .

A Low-Energy Asynchronous FFT/IFFT Processor for Hearing Aid Applications

Kwen-Siong Chong, B.-H. Gwee, J.S. Chang, 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline

Kwen-Siong Chong, Bah-Hwee Gwee, Rong Zhou, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2013, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack

Ali Akbar Pammu, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, 2016, 2016 International Symposium on Integrated Circuits (ISIC).

Low-voltage micropower multipliers with reduced spurious switching

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications

Kwen-Siong Chong, Bah-Hwee Gwee, Nan Liu, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Secure Data-Toggling SRAM for Confidential Data Protection

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2020, ISCAS.

Low Power Asynchronous Circuit Design: An FFT/IFFT Processor

Kwen-Siong Chong, Bah-Hwee Gwee, 2010 .

Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design

Wei Shu, Kwen-Siong Chong, Bah-Hwee Gwee, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Analytical delay variation modeling for evaluating sub-threshold synchronous/asynchronous designs

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells

Kwen-Siong Chong, Bah-Hwee Gwee, Chao Wang, 2019, 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST).

A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2017 .

Interceptive side channel attack on AES-128 wireless communications for IoT applications

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki, Japan, November 17-20, 2014

Kong-Pang Pun, Kwen-Siong Chong, Bah-Hwee Gwee, 2014, APCCAS.

A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2016, 2016 IEEE International Conference on Networking, Architecture and Storage (NAS).

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors

Kwen-Siong Chong, Bah-Hwee Gwee, J.S. Chang, 2007, IEEE Journal of Solid-State Circuits.

A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information

Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee, 2019, IEEE Transactions on Dependable and Secure Computing.

Low-voltage micropower asynchronous multiplier for hearing instruments

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits

Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

An ultra-low power asynchronous quasi-delay-insensitive (QDI) sub-threshold memory with bit-interleaving and completion detection

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

A comparative study on asynchronous Quasi-Delay-Insensitive templates

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Counteracting differential power analysis: Hiding encrypted data from circuit cells

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process

Kwen-Siong Chong, Joseph Sylvester Chang, Ne Kyaw Zwa Lwin, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2015, IET Circuits Devices Syst..

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller

Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Joseph S. Chang, 2020, ISCAS.

Low energy 16-bit Booth leapfrog array multiplier using dynamic adders

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2007, IET Circuits Devices Syst..

A Low-Voltage Micropower Asynchronous Multiplier With Shift–Add Multiplication Approach

Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2021, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Normalized Differential Power Analysis - for Ghost Peaks Mitigation

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron

Kwen-Siong Chong, Chao Wang, Guoyi Yu, 2021, 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS).

A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection

Kwen-Siong Chong, Bah-Hwee Gwee, Weng-Geng Ho, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures

Kwen-Siong Chong, Bah-Hwee Gwee, Jun-Sheng Ng, 2021, IEEE Transactions on Information Forensics and Security.

An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning

Kwen-Siong Chong, Chao Wang, Guoyi Yu, 2021, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.