Jason C. S. Woo

发表

Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs

Ying-Che Tseng, W. M. Huang, M. Mendicino, 2001 .

Deeply scaled VLSI analog transistor design and optimization

Peng Lu, Jason C. S. Woo, Po-Yen Chien, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

High performance sub-0.1 /spl mu/m SOI polysilicon spacer gate MOSFETs using large angle tilted implant for drain engineering

Jason C. S. Woo, Kun H. To, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Optimizing the fabrication process for high performance graphene field effect transistors

Ming Zhang, Yanjie Wang, Jason C. S. Woo, 2012, Microelectron. Reliab..

Analysis of edge effects in the mesa isolated nMOS SOI

James R. Collett, Jason C. S. Woo, James S. Cable, 1996, 1996 IEEE International SOI Conference Proceedings.

The impact of SOI MOSFETs on low power digital circuits

Ying-Che Tseng, Jason C. S. Woo, Steven C. Chin, 1997, ISLPED '97.

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Subramanian S. Iyer, Jason C. S. Woo, Faraz Khan, 2017, IEEE Electron Device Letters.

Temperature dependence of AC floating body effects in PD SOI nMOS

Philip D. Welch, W. M. Huang, Ying-Che Tseng, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Design Issues for Sub-100nm Analog CMOS

Jason C. S. Woo, Mayank Garg, Sushant S. Suryagandh, 2003 .

An alternative gate electrode material of fully depleted SOI CMOS for low power applications

Krishna C. Saraswat, Jason C. S. Woo, T. C. Hsiao, 1997, 1997 IEEE International SOI Conference Proceedings.

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Jason C. S. Woo, J. Woo, M. Song, 1997 .

A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping

Souvik Mahapatra, Juzer Vasi, V. Ramgopal Rao, 1999 .

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

J.M.C. Stork, Zhiping Yu, A. Inani, 1999 .

AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's

Ying-Che Tseng, Jason C. S. Woo, D. J. Monk, 1999 .

Ammonium Hydroxide Effect on Low-Temperature Wafer Bonding Energy Enhancement

Manfred Reiche, Jason C. S. Woo, Y.-L. Chao, 2005 .

A temperature-dependent MOSFET inversion layer carrier mobility model for device and circuit simulation

Jason C. S. Woo, Baohong Cheng, J. Woo, 1997 .

A new approach to implement 0.1 /spl mu/m MOSFET on thin-film SOI substrate with self-aligned source-body contact

Jason C. S. Woo, V.M.C. Chen, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length

Jason C. S. Woo, Sungkwon Hong, Seong-Dong Kim, 2002 .

Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

V. Ramgopal Rao, Jason C. S. Woo, J. Vasi, 2002 .

In-plane microactuator for fluid control application

Chih-Ming Ho, Chang-Jin Kim, Jason C. S. Woo, 1998, Proceedings MEMS 98. IEEE. Eleventh Annual International Workshop on Micro Electro Mechanical Systems. An Investigation of Micro Structures, Sensors, Actuators, Machines and Systems (Cat. No.98CH36176.

Optimization and realization of sub 100nm Channel length lateral Asymmetric Channel P-MOSFETS

V. Ramgopal Rao, Jason C. S. Woo, J. Vasi, 2000 .

Two-dimensional analytic modeling of very thin SOI MOSFETs

Jason C. S. Woo, P. K. Vasudev, J. Woo, 1990 .

Extraction of gate dependent source/drain resistance and effective channel length in MOS devices at 77 K

Jason C. S. Woo, C. Y. Hwang, Tsung-Chia Kuo, 1995 .

Nickel Silicide Work Function Tuning Study In Metal-Gate CMOS Applications

Jason C. S. Woo, Y.-L. Chao, Grant Z. Pan, 2004 .

High performance graphene FETs with self-aligned buried gates fabricated on scalable patterned ni-catalyzed graphene

Jason C. S. Woo, Ya-Hong Xie, Bo-Chao Huang, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

ASYMMETRIC TUNNELING SOURCE MOSFETS: A NOVEL DEVICE SOLUTION FOR SUB-100NM CMOS TECHNOLOGY

Jason C. S. Woo, R. Jhaveri, J. Woo, 2006 .