S. Martin

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations

E. Vianello, F. Andrieu, B. Giraud, 2022, ArXiv.

An 8 Mbit DRAM design using a 1 Tbulk cell

R. Ranica, A. Villaret, P. Candelier, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..