B. Chan

发表

A Scalable One Dimensional Silicon Qubit Array with Nanomagnets

T. Ivanov, P. Matagne, B. Govoreanu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability

F. M. Bufler, F. Inoue, R. Ritzenthaler, 2018, IEEE Transactions on Electron Devices.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2021, 2021 Symposium on VLSI Technology.

Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

A. Hikavyy, E. Rosseel, K. Devriendt, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

A flexible 300 mm integrated Si MOS platform for electron- and hole-spin qubits exploration

T. Ivanov, L. Goux, B. Govoreanu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

90nm W\Al2O3\TiW\Cu 1T1R CBRAM cell showing low-power, fast and disturb-free operation

L. Goux, A. Fantini, M. Jurczak, 2013, 2013 5th IEEE International Memory Workshop.

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

H. Mertens, R. Ritzenthaler, Z. Tao, 2020, 2020 IEEE Symposium on VLSI Technology.

FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3

Zheng Tao, Boon Teik Chan, Liping Zhang, 2020, Advanced Lithography.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, IEEE Transactions on Electron Devices.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster

A. Jourdain, G. Beyer, E. Beyne, 2021, 2021 Symposium on VLSI Technology.

Middle-of-line plasma dry etch challenges for buried power rail integration

H. Mertens, N. Horiguchi, A. Veloso, 2022, Advanced Lithography.

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

Middle-of-line plasma dry etch challenges for CFET integration

H. Mertens, Z. Tao, N. Horiguchi, 2023, Advanced Lithography.

Buried power rail integration for CMOS scaling beyond the 3 nm node

H. Mertens, Z. Tao, G. Mannaert, 2022, Advanced Lithography.

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

A. Jourdain, G. Beyer, E. Beyne, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

H. Mertens, Z. Tao, K. Devriendt, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

H. Mertens, A. Hikavyy, Z. Tao, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2022, 2022 International Electron Devices Meeting (IEDM).

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells

D. Tsvetanova, N. Horiguchi, J. Ryckaert, 2022, International Electron Devices Meeting.

3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters

A. Hikavyy, G. Mannaert, E. Rosseel, 2020, 2020 IEEE Symposium on VLSI Technology.

Challenges for spacer and source/drain cavity patterning in CFET devices

H. Mertens, G. Mannaert, S. Demuynck, 2023, Advanced Lithography.

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond

F. M. Bufler, H. Mertens, R. Ritzenthaler, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Integration of a Stacked Contact MOL for Monolithic CFET

O. Richard, N. Horiguchi, K. Vandersmissen, 2023, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).