Jianguo Yang

发表

Non-volatile In Memory Dual-Row X(N)OR Operation with Write Back Circuit Based on 1T1C FeRAM

Ming Liu, H. Lv, Q. Luo, 2020, 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).

Oxide‐Based Electrolyte‐Gated Transistors for Spatiotemporal Information Processing

Qi Liu, Ming Liu, H. Lv, 2020, Advanced materials.

A highly CMOS compatible hafnia-based ferroelectric diode

Qi Liu, H. Lv, Meilin Liu, 2020, Nature Communications.

Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy

H. Lv, Bo Peng, Yongkang Han, 2022, Micromachines.

24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference

H. Lv, Ming Liu, Xiaoxin Xu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Unified 0.75pJ/Bit TRNG and Attack Resilient 2F2/Bit PUF for Robust Hardware Security Solutions with 4-layer Stacking 3D NbOx Threshold Switching Array

Qi Liu, H. Lv, Meilin Liu, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Complementary Memory Cell Based on Field-Programmable Ferroelectric Diode for Ultra-Low Power Current-SA Free BNN Applications

Qi Liu, H. Lv, Ming Liu, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key

Yuejun Zhang, Ming Liu, Xiaoyang Zeng, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A highly CMOS compatible hafnia-based ferroelectric diode

Qi Liu, H. Lv, Meilin Liu, 2020, Nature Communications.

Binary Convolutional Neural Network Based on 3d Field-Programmable Ferroelectric Diode Array

H. Lv, Ming Liu, Jiezhi Chen, 2020, SSRN Electronic Journal.

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Jianguo Yang, Jingang Wu, Yinyin Lin, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance

Xiaoxin Xu, Ruijun Lin, Jianguo Yang, 2023, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 1T2C FeCAP-Based In-Situ Bitwise X(N)OR Logic Operation with Two-Step Write-Back Circuit for Accelerating Compute-In-Memory

H. Lv, Qiao Hu, Yuling Zhao, 2021, Micromachines.

Quantitative Analysis on Resistance Fluctuation of Resistive Random Access Memory by Low Frequency Noise Measurement

Ming Liu, H. Lv, Q. Luo, 2021, IEEE Electron Device Letters.

First Demonstration of OxRRAM Integration on 14nm FinFet Platform and Scaling Potential Analysis towards Sub-10nm Node

Qi Liu, Ming Liu, H. Lv, 2020, International Electron Devices Meeting.

Design and Simulation Analysis of a 3TnC MLC FeRAM Using a Nondestructive Readout and Offset-Canceled Sense Amplifier for High-Density Storage Applications

Bo Peng, Jianguo Yang, Donglin Zhang, 2023, Micromachines.

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques

Meng-Fan Chang, Xiaoxin Xu, Ming Liu, 2020, 2020 IEEE Symposium on VLSI Circuits.

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

H. Lv, Bo Peng, Yongkang Han, 2021, Micromachines.

A Novel PUF Using Stochastic Short-Term Memory Time of Oxide-Based RRAM for Embedded Applications

Ming Liu, H. Lv, Xiaoyang Zeng, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

Ming Liu, H. Lv, Xiaoyang Zeng, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI

Fei Wang, Zhongrui Wang, Xiaoxin Xu, 2023, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.02% Accuracy Loss Voltage-Mode Parallel Sensing Scheme for RRAM-Based XNOR-Net Application

Yue Cao, Xiaoxin Xu, Jie Yu, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier

H. Lv, Yue Cao, Meilin Liu, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

Enabling RRAM-Based Brain-Inspired Computation by Co-design of Device, Circuit, and System

Ming Liu, Qi Liu, Q. Luo, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction

G. Chen, R. Huang, X. Y. Xue, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme

Qi Liu, Ming Liu, H. Lv, 2021, Symposium on VLSI Technology.

A RRAM-Based True Random Number Generator with 2T1R Architecture for Hardware Security Applications

Bo Peng, Jianguo Yang, Qiqiao Wu, 2023, Micromachines.