H. Fujiwara

发表

An inter-die variability compensation scheme for 0.42-V 486-kb FD-SOI SRAM using substrate control

H. Fujiwara, T. Takeuchi, Yu. Otake, 2008, 2008 IEEE International SOI Conference.

Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip

H. Fujiwara, T.E. Yu, T. Yoneda, 2007, 16th Asian Test Symposium (ATS 2007).

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

H. Fujiwara, Y. Nakamura, T. Clouqueur, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

S. Mourad, H. Fujiwara, 2004, Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510).

A non-scan DFT method at register-transfer level to achieve complete fault efficiency

H. Fujiwara, S. Ohtake, H. Wada, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Discriminating robot system for carnation seedling with fuzzy logic

H. Fujiwara, 1991 .

Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost

Dong Xiang, H. Fujiwara, K. Chakrabarty, 2007, 16th Asian Test Symposium (ATS 2007).

Test Application Time Reduction with a Dynamically Reconfigurable Scan Tree Architecture

Y. Bonhomme, H. Fujiwara, T. Yoneda, 2005 .

Impact of divided static random access memory considering data aggregation for wireless sensor networks

C. Ohta, H. Fujiwara, T. Takeuchi, 2008, 2008 7th Asia-Pacific Symposium on Information and Telecommunication Technologies.

Performance evaluation of a multi-stage network event detection scheme against DDoS attacks

Tutomu Murase, Yukinobu Fukushima, Ryohei Fujimaki, 2008, 2008 7th Asia-Pacific Symposium on Information and Telecommunication Technologies.

Which is the best dual-port SRAM in 45-nm process technology? — 8T, 10T single end, and 10T differential —

H. Fujiwara, M. Yoshimoto, H. Kawaguchi, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code

C. Ohta, H. Fujiwara, T. Takeuchi, 2007, 2007 International Conference on Sensor Technologies and Applications (SENSORCOMM 2007).

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

H. Fujiwara, M. Yoshimoto, H. Kawaguchi, 2007, 2007 IEEE Symposium on VLSI Circuits.

Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture

Dong Xiang, Yang Zhao, Jiaguang Sun, 2006, 2006 15th Asian Test Symposium.

A study of wheeled mobile robot with a compliant mechanism for climbing up a step

H. Fujiwara, H. Ookubo, E. Nakano, 1997, Proceedings of IEEE/ASME International Conference on Advanced Intelligent Mechatronics.

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults

H. Fujiwara, S. Ohtake, H. Fujiwara, 2007, 16th Asian Test Symposium (ATS 2007).

ON THE ACCELERATION OF TEST GENERATION ALGORlTHMS

H. Fujiwara, H. Fujiwara, T. Shimono, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

Improving test quality of scan-based BIST by scan chain partitioning

Dong Xiang, H. Fujiwara, Jia-Guang Sun, 2003, 2003 Test Symposium.

A framework for low complexity static learning

H. Fujiwara, E. Gizdarski, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).