M. Cordeau

Impact of roughness of TiN bottom electrode on the forming voltage of HfO2 based resistive memories

E. Jalaguier, S. Martinie, S. Bernasconi, 2020 .

ECD seed copper layer for seed enhancement in advanced interconnects

P. Haumesser, G. Passemard, T. Ritzdorf, 2003 .

Copper post-electroplating anneal: evaluation of in-line vs. furnace anneal on layer properties

S. Maitrejean, P. Haumesser, T. Mourier, 2003 .

Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

Yves Morand, Christian Arvet, T. Mourier, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

Porous low k pore sealing process study for 65 nm and below technologies

S. Maitrejean, R. Pantel, P. Haumesser, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

300 mm InGaAsOI substrate fabrication using the Smart CutTM technology

F. Fournel, C. Morales, J. Widiez, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

InGaAs-OI Substrate Fabrication on a 300 mm Wafer

S. Sollier, J. Widiez, F. Fournel, 2016 .

Correlation between electromigration and Cu-contact angle after de-wetting

T. Mourier, J. Dupuy, M. Cordeau, 2006 .

Copper-SiOC-AirGap integration in a double level metal interconnect

Y. Morand, M. Assous, L. Ulmer, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

Copper metallization for advanced interconnects: the electrochemical revolution

S. Maitrejean, P. Haumesser, G. Passemard, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).