A. Yabata

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system

M. Koyanagi, K. Kiyoyama, H. Hashimoto, 2012, 2012 International Electron Devices Meeting.

Chip-based hetero-integration technology for high-performance 3D stacked image sensor

Kang Wook Lee, M. Koyanagi, T. Kamada, 2012, 2012 2nd IEEE CPMT Symposium Japan.

Characteristics of Very High-Aspect-Ratio Contact Hole Etching

Naokatsu Ikegami, Takayuki Matsui, Yasuhiro Horiike, 1997 .

Vertical Profile Control in Ultrahigh-Aspect-Ratio Contact Hole Etching with 0.05-µm-Diameter Range

N. Hirashita, J. Kanamori, A. Yabata, 1998 .