Shi-Yu Huang

A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation

Ya-chin King, Cheng-Hsiao Lai, Cheng-Hsiao Lai, 2006, IEEE Sensors Journal.

Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)

Shi-Yu Huang, Ya-Chun Lai, 2009, IEEE Journal of Solid-State Circuits.