L. Black

CMOS Fabricated by Hybrid-Orientation Technology (HOT)

C. D. Sheraw, S. Narasimha, P. Agnello, 2007, 2007 International Workshop on Electron Devices and Semiconductor Technology (EDST).

(110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering

S. Narasimha, E. Maciejewski, E. Leobandung, 2007, 2007 IEEE International Electron Devices Meeting.

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

J. Gill, D. Mocuta, D. Greenlaw, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Dual stress liner enhancement in hybrid orientation technology

M. Ieong, T. Kanarsky, D. Chidambarrao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

D. Mocuta, E. Maciejewski, E. Leobandung, 2008, 2008 IEEE International Electron Devices Meeting.

Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

M. Ieong, Z. Ren, O. Dokumaci, 2005, 2005 IEEE International SOI Conference Proceedings.