K. Henson

An investigation of the electron tunneling leakage current through ultrathin oxides/high-k gate stacks at inversion conditions

B. Govoreanu, P. Blomme, J. Van Houdt, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

Layout density analysis of FinFETs

N. Collaert, S. Biesemans, K.G. Anil, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics

Rita Rooyackers, Wim Deweerd, Tom Schram, 2005 .

Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants

N. Collaert, M. Rosmeulen, K. De Meyer, 2000, IEEE Electron Device Letters.

High k dielectric materials prepared by atomic layer CVD

Richard Carter, Guido Groeseneken, Wilfried Vandervorst, 2001 .

An effective model for analysing tunneling gate leakage currents through ultrathin oxides and high-k gate stacks from Si inversion layers

Pieter Blomme, Jan Van Houdt, Kristin De Meyer, 2004 .

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

E. Luckowski, H. Bu, V. Narayanan, 2008, 2008 IEEE International Electron Devices Meeting.

Leakage optimization of ultra-shallow junctions formed by solid phase epitaxial regrowth

Karen Maex, Wilfried Vandervorst, Jorge Kittl, 2004 .

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

E. Augendre, A. Veloso, S. Biesemans, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..