Edwin Thaller

Method and apparatus for extracting a clock frequency underlying a data stream

Patrizia Greco, Andreas Dipl.-Ing. Steinschaden, Edwin Thaller, 2002 .

Digital Polar Transmitter Architecture suitable for multi-core SoC Integration in 65 nm CMOS Technology

Stefan Heinen, Stefan Van Waasen, Edwin Thaller, 2012 .

Digital compensation of DC-DC converter voltage ripple for Switched-Capacitor Power Amplifiers

Mario Huemer, Michael Lunglmayr, Daniel Gruber, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE

Andrea Bevilacqua, Andrea Neviani, Edwin Thaller, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Digital pll clock with automatic alignment

Edwin Thaller, Giuseppe Li Puma, Stefano Marsili, 2012 .

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

Ashoke Ravi, Kamran Azadet, Nir Geron, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).