Davide Vecchi

Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCs

Giovanni Chiorboli, Andrea Boni, Cristiano Azzolini, 2009, Circuits Syst. Signal Process..

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS

Jan Mulder, Jan R. Westra, Davide Vecchi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS

Andrea Boni, Davide Vecchi, Matteo Parenti, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS

Han Yan, Sijia Wang, Jan Mulder, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

DAC calibration by weighting capacitor rotation in a pipelined ADC

Giovanni Chiorboli, Davide Vecchi, Carlo Morandi, 2005, Circuits, Signals, and Systems.

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers

Xiaodong Liu, Sijia Wang, Jan Mulder, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS

Jan Mulder, Jan R. Westra, Davide Vecchi, 2011, IEEE Journal of Solid-State Circuits.

An 800MS/s dual-residue pipeline ADC in 40nm CMOS

Jan Mulder, Jan R. Westra, Davide Vecchi, 2011, 2011 IEEE International Solid-State Circuits Conference.