Jessy Clédière

发表

What do S-boxes Say in Differential Side Channel Attacks?

Cécile Canovas, Jessy Clédière, J. Clédière, 2005, IACR Cryptol. ePrint Arch..

A Proposition for Correlation Power Analysis Enhancement

Jean-Louis Lacoume, Bruno Robisson, Cécile Canovas, 2006, CHES.

Novel Approaches for Improving the Power Consumption Models in Correlation Analysis

Cécile Canovas, Jessy Clédière, Thanh-Ha Le, 2007, IACR Cryptol. ePrint Arch..

Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2009, 2009 27th IEEE VLSI Test Symposium.

Nanofocused X-Ray Beam to Reprogram Secure Circuits

Jessy Clédière, Stéphanie Anceau, Pierre Bleuet, 2017, CHES.

From Code Review to Fault Injection Attacks: Filling the Gap Using Fault Model Inference

Cécile Canovas, Jessy Clédière, Marie-Laure Potet, 2015, CARDIS.

Security testing for hardware products: the security evaluations practice

Jessy Clédière, Alain Merle, 2005, 11th IEEE International On-Line Testing Symposium.

Noise Reduction in Side Channel Attack Using Fourth-Order Cumulant

Jean-Louis Lacoume, Jessy Clédière, Christine Servière, 2007, IEEE Transactions on Information Forensics and Security.

Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism

Jean-Max Dutertre, Assia Tria, Jessy Clédière, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

An overview of side channel analysis attacks

Cécile Canovas, Jessy Clédière, Thanh-Ha Le, 2008, ASIACCS '08.

Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter

Jean-Max Dutertre, Bruno Robisson, Jessy Clédière, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor

Cécile Canovas, Jessy Clédière, Philippe Elbaz-Vincent, 2013, J. Electron. Test..

How can Signal Processing benefit Side Channel Attacks

Jean-Louis Lacoume, Jessy Clédière, Thanh-Ha Le, 2007 .

Analysis of a fault injection mechanism related to voltage glitches using an on-chip voltmeter

Jean-Max Dutertre, Jessy Clédière, Bruno Robisson, 2014 .

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2010, 2010 15th IEEE European Test Symposium.

Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis

Denis Réal, Frédéric Valette, Cécile Canovas, 2008, 2008 Design, Automation and Test in Europe.

Influence of the temperature on true random number generators

Denis Réal, Cécile Canovas, Jessy Clédière, 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

From physical stresses to timing constraints violation

Jean-Max Dutertre, Assia Tria, Jessy Clédière, 2013 .

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

Régis Leveugle, Jessy Clédière, Paolo Maistri, 2011, Journal of Cryptology.

Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Efficient Solution for Misalignment of Signal in Side Channel Analysis

Jean-Louis Lacoume, Jessy Clédière, Christine Servière, 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA

Frédéric Valette, Régis Leveugle, Jessy Clédière, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

Evidence of an information leakage between logically independent blocks

Jean-Max Dutertre, Bruno Robisson, Assia Tria, 2015, CS2@HiPEAC.

EM Fault Model Characterization on SoCs: From Different Architectures to the Same Fault Model

Jessy Clédière, Thomas Trouchkine, Guillaume Bouffard, 2021, 2021 Workshop on Fault Detection and Tolerance in Cryptography (FDTC).