M. Balseanu

Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Wen-Chin Lee, S. Demuynck, Jianxin Lei, 2008, IEEE Transactions on Electron Devices.

A reliable and manufacturable method to induce a stress of >1 GPa on a P-channel MOSFET in high volume manufacturing

G. Karunasiri, R. Arghavani, H. M'Saad, 2006, IEEE Electron Device Letters.