H. Nakamura

A design concept for the low turn-off loss 4.5 kV trench IGBT

Akio Uenishi, Shigeru Kusunoki, T. Nitta, 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

Evaluation of thick silicon dioxides grown on trench MOS gate structures

K. Nakamura, Tadaharu Minato, M. Harada, 1996, 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings.

A simple and effective carrier lifetime evaluation method with diode test structures in IGBT

S. Aono, A. Uenishi, M. Harada, 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.

Advantages of thick CVD gate oxide for trench MOS gate structures

Shigeru Kusunoki, K. Nakamura, M. Harada, 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).