R. Murgai

发表

Logic synthesis for programmable gate arrays

R. Brayton, A. Sangiovanni-Vincentelli, N. Shenoy, 1990, 27th ACM/IEEE Design Automation Conference.

R. Brayton, A. Sangiovanni-Vincentelli, R. Murgai, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Efficient global fanout optimization algorithms

R. Murgai, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

A Delay Metric for RC Circuits Based on the Weibull Distribution

Luciano Lavagno, Malgorzata Marek-Sadowska, Rajeev Murgai, 2004 .

Statistical analysis of hold time violations

Rajeev Murgai, William W. Walker, Ricardo Reis, 2010 .

Improved layout-driven area-constrained timing optimization by net buffering

Rajeev Murgai, R. Murgai, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Delay-constrained area recovery via layout-driven buffer optimization

Rajeev Murgai, R. Murgai, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Delay estimation and optimization of logic circuits: a survey

Rajeev Murgai, Masahiro Fujita, M. Fujita, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Performance directed synthesis for table look up programmable gate arrays

Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Rajeev Murgai, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Hardness of approximate two-level logic minimization and PAC learning with membership queries

R. Brayton, A. Sangiovanni-Vincentelli, R. Murgai, 2006, STOC '06.

Cube-packing and two-level minimization

A. Sangiovanni-Vincentelli, R.K. Brayton, R. Murgai, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

4.2 Mapping to Selector Functions 5 Conclusions and Future Work

R. Brayton, N. Shenoy, R. Murgai, 2022 .

Data Sequencing for Minimum-transition Transmission

Rajeev Murgai, Sriram C. Krishnan, Masahiro Fujita, 1997 .

Clock distribution architectures: a comparative study

Rajeev Murgai, William W. Walker, Hongyu Chen, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

SIS : A System for Sequential Circuit Synthesis

P. R. Stephan, E. M. Sentovich, R. Brayton, 1992 .

Improved logic synthesis algorithms for table look up architectures

Rajeev Murgai, Narendra V. Shenoy, R. Brayton, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Using complementation and resequencing to minimize transitions

Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Design and Analysis of "Tree+Local Meshes" Clock Architecture

Rajeev Murgai, Gustavo R. Wilke, G. Wilke, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

ADAMIN : Automated , Accurate Macromodelling of Digital Aggressors for Power and Ground Supply Noise Prediction

J. Roychowdhury, R. Murgai, Zhe Wang, 2022 .

Speeding Up Look-up-Table Driven Logic Simulation

Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose, 1999, VLSI.

Some recent advances in software and hardware logic simulation

Rajeev Murgai, Masahiro Fujita, M. Fujita, 1997, Proceedings Tenth International Conference on VLSI Design.