Shiro Kamohara

发表

Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters

Mikako Miyama, Shiro Kamohara, 2000, ASP-DAC.

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM

Nobuyuki Sugii, Toshitsugu Sakamoto, Takumi Hasegawa, 2015, IEEE Micro.

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

Koji Nii, Shinji Tanaka, Makoto Yabuuchi, 2017, 2017 Symposium on VLSI Technology.

A new method for predicting distribution of DRAM retention time

Shiro Kamohara, Yuki Mori, R.-I. Yamada, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

A 44μW/10MHz minimum power operation of 50K logic gate using 65nm SOTB devices with back gate control

Cong-Kha Pham, Nobuyuki Sugii, Koichiro Ishibashi, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2016, IEEE Transactions on Electron Devices.

Quantitative analysis of SILCs (stress-induced leakage currents) based on the inelastic trap-assisted tunneling model

Donggun Park, Chenming Hu, Katsuhiko Kubota, 1999, Advanced Lithography.

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive

Takumi Hasegawa, Shiro Kamohara, Hideki Makiyama, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

SOTB technology, which enables perpetually reliable CPU for IoT applications

Kazutoshi Kobayashi, Nobuyuki Sugii, Koichiro Ishibashi, 2015, 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

QUANTITATIVE ANALYSIS OFRANDOMTELEGRAPH SIGNALS AS FLUCTUATIONS OFTHRESHOLD VOLTAGESINSCALEDFLASHMEMORYCELLS

Hideaki Kurata, Shiro Kamohara, Taro Osabe, 2007 .

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM

Nobuyuki Sugii, Toshitsugu Sakamoto, Takumi Hasegawa, 2015, 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII).

An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

Koji Nii, Shinji Tanaka, Yohei Sawada, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes

Naoki Kitai, Kenichi Osada, Takayuki Kawahara, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis

Isao Miyazaki, Shiro Kamohara, Yoshiyuki Kaneko, 2011, IEICE Trans. Electron..

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Nobuyuki Sugii, Koichiro Ishibashi, Toshiro Hiramoto, 2014 .

Statistical analysis of four write stability metrics in fully depleted silicon-on-thin-BOX (SOTB) and bulk SRAM cells at low supply voltage

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A 400mV 0.59mW low-power CAM-based pattern matching system on 65nm SOTB process

Duc-Hung Le, Cong-Kha Pham, Hong-Thu Nguyen, 2015, TENCON 2015 - 2015 IEEE Region 10 Conference.

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

Duc-Hung Le, Cong-Kha Pham, Xuan-Thuan Nguyen, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

MOSFET Carrier Mobility Model Based on the Density-of-State at the DC-Centroid in the Quantized Inversion Layer

Kai Chen, Ya-Chin King, Shiro Kamohara, 1997 .

Robust design of 0.18 /spl mu/m ASIC MOSFETs using Taguchi method with TCAD

Y. Ohji, Shiro Kamohara, M. Kawakami, 2001, 2001 6th International Workshop on Statistical Methodology (Cat. No.01TH8550).

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode

Hideharu Amano, Cong-Kha Pham, Kazutoshi Kobayashi, 2015 .

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

Koji Nii, Shinji Tanaka, Makoto Yabuuchi, 2017, 2017 Symposium on VLSI Circuits.

Variation; key issue of the advanced CMOS & LSI's

Akio Nishida, Toshiro Hiramoto, Shiro Kamohara, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

Nobuyuki Sugii, Masaharu Kobayashi, Toshiro Hiramoto, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A 361nA thermal run-away immune VBB generator using dynamic substrate controlled charge pump for ultra low sleep current logic on 65nm SOTB

Nobuyuki Sugii, Koichiro Ishibashi, Shiro Kamohara, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Studies of Coulomb Blockade , Single-Trangister Dynamic Memory , and Oxide Trap Charge State Based on the Random Telegraph Noise Modeling

Kiyotaka Imai, Chenming Hu, Shiro Kamohara, 1997 .

Statistical BSIM3 model parameter extraction and fast/slow model parameter determination for high speed SRAM parametric yield estimation

Kousuke Okuyama, T. Akioka, Mikako Miyama, 2000, 2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Repair yield simulation with iterative critical area analysis for different types of failure

Kazunori Nemoto, Kousuke Okuyama, Shiro Kamohara, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors

Akio Nishida, Toshiro Hiramoto, Shiro Kamohara, 2009 .

Anomalous Leakage Current Model for Retention Failure in Flash Memories

Katsuhiko Kubota, Hitoshi Kume, Shiro Kamohara, 1999 .

Origin of Larger Drain Current Variability in N-Type Field-Effect Transistors Analyzed by Variability Decomposition Method

Tohru Mogami, Akio Nishida, Toshiro Hiramoto, 2010 .

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Akio Nishida, Toshiro Hiramoto, Kiyoshi Takeuchi, 2009 .

High-Temperature Properties of Drain Current Variability in Scaled Field-Effect Transistors Analyzed by Decomposition Method

Tohru Mogami, Akio Nishida, Toshiro Hiramoto, 2011 .

Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal-Oxide-Semiconductor Field-Effect Transistors in 45 nm Technology and Beyond

Akio Nishida, Toshiro Hiramoto, Shiro Kamohara, 2009 .